5 December 2005 Simulation and design of Si double-photodetector for monolithic OEIC in standard CMOS technology
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Proceedings Volume 6020, Optoelectronic Materials and Devices for Optical Communications; 602031 (2005); doi: 10.1117/12.635721
Event: Asia-Pacific Optical Communications, 2005, Shanghai, China
Abstract
Silicon photodetector can be integrated with all kinds of Silicon circuits to get monolithic OEIC. A CMOS-process-compatible silicon double-photodetector with structures of P+/N-well and N-well/P-substrate, called PD1 and PD2 respectively, is designed in this paper. The theoretical absolute spectral response and response speed of this double-photodetector are calculated and analyzed. Simulation results in 0.5um standard CMOS process show that the responsivity of the double-photodetector is above 0.2A/W from 400 to 900nm wavelength range without ARC (Anti-Reflection-Coating). Both the effects of the insulated medium layers (SiO2 and Si3N4) in CMOS process and reverse voltage on spectral responsivity are also discussed. When the optical window area is 16.54μmx16.54μm2, the capacitance of PD1 is about 100fF at a reverse voltage of 2.5V. Yet the capacitance of PD2 is almost 1/10 of PD1. With a load-resistor of 50Ω, the response speeds of PD1, PD2 and double-photodetector are 0.628, 2.04 and 2.05ns at 650nm wavelength (corresponding bandwidth about 276MHz, 85MHz and 84.7MHz), respectively. Finally, the co-design of Monolithic OEIC is also discussed. A full CMOS monolithic OEIC for optical-disc signal pickup is designed with this double-detector.
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Jiantao Bian, Chao Chen, Sheng Xie, "Simulation and design of Si double-photodetector for monolithic OEIC in standard CMOS technology", Proc. SPIE 6020, Optoelectronic Materials and Devices for Optical Communications, 602031 (5 December 2005); doi: 10.1117/12.635721; https://doi.org/10.1117/12.635721
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KEYWORDS
Silicon

Photonic integrated circuits

CMOS technology

Photodetectors

Capacitance

Sensors

Diffusion

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