A real-time asymmetric multiprocessor reconfigurable system-on-chip architecture

Xin Xie; John A. Williams; Neil W. Bergmann

doi:10.1117/12.638216

5 January 2006 A real-time asymmetric multiprocessor reconfigurable system-on-chip architecture

Xin Xie, John A. Williams, Neil W. Bergmann

Proceedings Volume 6035, Microelectronics: Design, Technology, and Packaging II; 603508 (2006) https://doi.org/10.1117/12.638216
Event: Microelectronics, MEMS, and Nanotechnology, 2005, Brisbane, Australia

Abstract

We propose an asymmetric multi-processor SoC architecture, featuring a master CPU running uClinux, and multiple loosely-coupled slave CPUs running real-time threads assigned by the master CPU. Real-time SoC architectures often demand a compromise between a generic platform for different applications, and application-specific customizations to achieve performance requirements. Our proposed architecture offers a generic platform running a conventional embedded operating system providing a traditional software-oriented development approach, while multiple slave CPUs act as a dedicated independent real-time threads execution unit running in parallel of master CPU to achieve performance requirements. In this paper, the architecture is described, including the application / threading development environment. The performance of the architecture with several standard benchmark routines is also analysed.

Citation Download Citation

Xin Xie, John A. Williams, and Neil W. Bergmann "A real-time asymmetric multiprocessor reconfigurable system-on-chip architecture", Proc. SPIE 6035, Microelectronics: Design, Technology, and Packaging II, 603508 (5 January 2006); https://doi.org/10.1117/12.638216

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