This paper presents a static design methodology dedicated to ultra low power (Vdd < 1V ) analog circuits. This methodology based on the EKV 2.0 MOS model, tuned with non uniform substrate doping correction and rigorous derivation of the EKV 3.0 MOS model, provides continuous over inversion levels (weak - moderate - strong inversion) equations in conduction as in saturation modes. Fundamental parasitic effects such as mobility reduction due to vertical field are therefore integrated with highlights of newer EKV versions. Furthermore, this methodology provides a tool for integrating easily this improvement during conception phase. A chart links the normalization current IS to the gate voltage VG and the pinch off voltage VP , allows the use of EKV 2.0 tuned formulas for designing analog circuits without inversion level constraint. It results in a good accuracy over all regions of MOS operation, including moderate inversion where neither weak-inversion nor traditional strong inversion MOS hand analysis is applicable. Starting from proposed equations, or standard asymptotes when strong constraints of weak/strong inversion are imposed, the use of a mathematical computing software results in the creation of wholes of solutions which describe completely the design. It is thus possible to make a complete study of a static circuit, independent of inversion level so as to make optimum design. Supply voltage and silicium area can thus be unambiguously optimized, without risk of running in circle as in "traditional" approaches. As an example, the self cascode PTAT voltage reference is studied with the methodology.