3 March 2006 Scaling VCSEL performance for 100terabits/s systems
Author Affiliations +
We evaluate VCSEL interconnects for next-generation High Productivity Computers in which hundreds of terabits of bandwidth are envisioned. We present results for VCSEL based links operating PAM-4 signaling using a commercial 0.13μm CMOS technology. We perform a complete link analysis of the Bit Error Rate, Q factor, random and deterministic jitter by measuring waterfall curves versus margins in time and amplitude. We demonstrate that VCSEL based PAM-4 can match or even improve performance over binary signaling under conditions of bandwidth limited 100meter multi-mode optical link at 5Gbps. We present the first sensitivity measurements for optical PAM-4 and compare it with binary signaling. An empirical relationship for VCSEL scaling versus bit rate and aperture is presented in order to explore reliability of VCSEL-based links. Reliability is found to degrade with aperture with a fourth order power law dependence.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
J. E. Cunningham, D. Beckman, Xuezhe Zheng, A. V. Krishnamoorthy, "Scaling VCSEL performance for 100terabits/s systems", Proc. SPIE 6124, Optoelectronic Integrated Circuits VIII, 61240O (3 March 2006); doi: 10.1117/12.658826; https://doi.org/10.1117/12.658826


Fast identification of highly distorted images
Proceedings of SPIE (January 27 2010)
Commercialization of Honeywell's VCSEL technology
Proceedings of SPIE (May 01 2000)
Estimating adders for a low density parity check decoder
Proceedings of SPIE (August 25 2006)
nLighten parallel optical modules
Proceedings of SPIE (May 01 2000)
3.2-Gb/s VCSEL driver implemented in 0.18-um CMOS
Proceedings of SPIE (February 17 2003)

Back to Top