CCD noises and their causes are analyzed. Methods to control these noises, such as Correlated Double Sampling (CDS), filtering, cooling, clamping, and calibration are proposed. To improve CCD sensor's performances, the IC, called Analog Front End (AFE), integration of CDS, clamping, Programmable Gain Amplifier (PGA), offset, and ADC, which can fulfill the CDS and analog-to-digital conversion, is employed to process the output signal of CCD. Based on the noise control approaches, the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator, for both CCD and AFE, and (2) interface, helping to analysis and transfer control command and status information between MCU controller and drive pulse generator, or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed, such as clock generator for CCD and AFE, MCU interface, AFE serial interface, output interface, CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip, Xilinx XC2C256-6-VQ100, with 20MHz pixel frequency, and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last, the design result is presented.