23 March 2006 Multi-level step and flash imprint lithography for direct patterning of dielectrics
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The dual damascene process used to generate copper interconnects requires many difficult processing steps. Back End Of Line (BEOL) processing using Step and Flash Imprint Lithography (SFIL) on a directly patternable dielectric material can dramatically reduce the number of processing steps. By using multi-level SFIL rather than photolithography, two levels of interconnect structure (trench and corresponding via) can be patterned simultaneously. In addition, the imprinted material can be a imprintable dielectric precursor rather than a resist, further reducing the total number of steps in the dual damascene process. This paper presents progress towards integrating multi-level SFIL into a copper CMP process flow at ATDF, Inc. in Austin, Texas. Until now, work has focused on multi-level imprint process development. This report focuses on the development of new imprintable dielectric precursors for use with the dual damascene imprint process. SFIL compatible dielectric precursors were synthesized and characterized for integration into the ATDF copper CMP process flow. SFIL requires properties not found in currently available semiconductor dielectrics such as low viscosity and rapid photo-induced polymerization. Inorganic/organic hybrid materials derived from sol-gel chemistry and polyhedral oligomeric silsesquioxane (POSS) structures show promise for this application. The properties of three different dielectric layers are compared. The viability of each material as an interlayer dielectric is discussed and the results of multi-level patterning, metal fill, and polish are shown.
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Frank Palmieri, Frank Palmieri, Michael D. Stewart, Michael D. Stewart, Jeff Wetzel, Jeff Wetzel, Jianjun Hao, Jianjun Hao, Yukio Nishimura, Yukio Nishimura, Kane Jen, Kane Jen, Colm Flannery, Colm Flannery, Bin Li, Bin Li, Huang-Lin Chao, Huang-Lin Chao, Soo Young, Soo Young, Woon Chun Kim, Woon Chun Kim, Paul S. Ho, Paul S. Ho, C. Grant Willson, C. Grant Willson, } "Multi-level step and flash imprint lithography for direct patterning of dielectrics", Proc. SPIE 6151, Emerging Lithographic Technologies X, 61510J (23 March 2006); doi: 10.1117/12.655604; https://doi.org/10.1117/12.655604

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