The EBIS data conversion system has been developed to be optimized for layout data of logic devices with Character Projection (CP) method. In the system, standard cells and memory cells are registered into a character database as keeping the hierarchy of cell pattern in the device pattern, so that a common CP aperture can be created for several logic devices. The order of EB shots are optimized to shorten the time of writing the patterns, small shots (sliver shots) create as few as possible, and the total number of EB shots are minimized for a specified CP aperture. The system was evaluated by processing ASIC devices of hp 180 nm, 130 nm and 90 nm nodes. The average processing time is about 1 hour with the average number of EB shots of 50 × 106 per a chip. The reduction rates of the number of shots from only conventional Variably Shaped Beam (VSB) to with CP were estimated about 80%, 45%, and 80% for the layers of front-end-of-line (FEOL), metal and via layers of back-end-of-line (BEOL), respectively.