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24 March 2006 Defect metrology challenges for the 45-nm technology node and beyond
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Without the ability to detect potential yield-limiting defects in-line, the yield learning cycle is severely crippled, compromising the financial success of chip makers. As design rules shrink, device yield is seriously affected by smaller size particle and patterned defects that were not important in the past. These mechanisms are becoming more difficult to detect with current defect detection tools and techniques. The optical defect inspection tools that are currently available do not adequately detect defects, while scanning electron microscope (SEM) based inspection tools are too slow. With each successive technology node, optical inspection becomes less capable relative to the previous technology. As sensitivity is increased to detect smaller defects, the nuisance defect rate increases commensurately. Line-edge roughness (LER) and subtle process variations are making it more difficult to detect defects of interest (DOI). Smaller defects mean smaller samples available for energy dispersive x-ray analysis (EDX), necessitating an improved or new methodology for elemental analysis. This paper reviews these and some other challenges facing defect metrology at the 45nm technology node and beyond. The challenges in areas of patterned and unpatterned wafer inspection, defect review, and defect characterization are outlined along with proposed solutions. It also provides an overview of several ongoing projects conducted at International SEMATECH Manufacturing Initiative (ISMI) to address these challenges.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dilip Patel, Jeffrey Hanrahan, Kyuhong Lim, Milton Godwin, Peter Figliozzi, and Dale Sheu "Defect metrology challenges for the 45-nm technology node and beyond", Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 615207 (24 March 2006);


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