As Critical Dimensions (CD) for semiconductor devices shrink to few tens of nanometers, the Line Edge Roughness (LER) or Line Width Roughness (LWR) becomes a critical issue because it can degrade resolution and linewidth accuracy  and causes fluctuations of transistors performances [2-8]. LER is currently calculated with top-view SEM images [9-10]. However, these values do not take into account the sidewall variation along the height of the feature (feature's geometry). Therefore, roughness information might get lost. In addition several issues impact the roughness measurement accuracy for example: blooming effect, resist slimming, algorithm used (...). Alternatively, the last generation of CD-AFM, [11,12] has been developed to measure pattern in three dimensions with a dynamic repeatability of around 1nm (3σ). By smartly tuning AFM parameters and choosing suitable AFM tips, CD, LER and LWR of both isolated lines and dense line are measured as a function of the position on the feature. This metrology technique can be used on a large range of materials: photoresist, silicon oxide and poly-silicon, without any pattern damage. Hence, it enables to fully characterize the evolution of the sidewall roughness after each technological step of a typical device fabrication.
In this paper we will compare CD-SEM and CD-AFM techniques as a mean to measure LER and LWR on real resist structures and hard-mask structures (SiO2) that show significant variations due to different chemical compositions or processes conditions. In order to well understand the limitations of each technique, we have generated and mixed various roughness amplitudes with various feature's shapes (different top rounding, sidewall angle...). Depending on the technique and feature's shapes, the roughness measurements trends are different which can lead to wrong process tuning and therefore degrade device performances at the end.