24 March 2006 Multilayer overlay metrology
Author Affiliations +
Abstract
A novel approach to overlay metrology, called Blossom, maximizes the number of layers measurable within a single optical field of view (FOV). As chip processing proceeds, each layer contributes a set of at least four marks, arranged symmetrically on concentric circles, to create a 90° rotationally invariant array of marks that "blossoms" to fill the FOV. Radial symmetry about the target center is maintained at each layer to minimize susceptibility to metrology lens aberrations. Overlay combinations among detectable marks within the target can be measured simultaneously. In the described embodiment, 28 distinct layers are represented within a 50μm square FOV. Thus, all the layers of a functional chip can be represented in a single target. Blossom achieves several benefits relative to overlay methods currently in practice: * Compression (>30X) of area required for overlay targets. * Nullification of within-target proximity effects. * Suppression of optical mark fidelity (OMF) errors. * Reduction of sensitivity to across-target detection noise.* Elimination of overlay error random walk among layers. * Reference mark redundancy for detection flexibility and robustness. * Integration of multi-layer and within-layer overlay control schema. * Simplification of overlay recipe creation and management. * Capture and visualization of overlay performance through the entire chip fabrication. Blossom results from 65-nm products in manufacturing are described.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
C. P. Ausschnitt, J. Morningstar, W. Muth, J. Schneider, R. J. Yerdon, L. A. Binns, N. P. Smith, "Multilayer overlay metrology", Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 615210 (24 March 2006); doi: 10.1117/12.657397; https://doi.org/10.1117/12.657397
PROCEEDINGS
10 PAGES


SHARE
KEYWORDS
Overlay metrology

Back end of line

Front end of line

Metrology

Tolerancing

Semiconducting wafers

Image processing

RELATED CONTENT


Back to Top