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24 March 2006 In-line semi-electrical process diagnosis methodology for integrated process window optimization of 65nm and below technology nodes
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Abstract
This paper presents the application of an innovative concept as potentially very powerful in-line diagnosis techniques in both process window optimization and yield enhancement for 65nm-and-below generations of technology. These applications were fulfilled with a novel methodology of the measurement and quantification of the grey levels on the SEM images and their correlation with the physical/electrical parameters of the semiconductor process steps. With these techniques and the few demonstrations, the virtual in-line semi-electrical measurement is proven to be a feasible technique in achieving technology development with lower cost and faster iteration cycle for continuous improvement. Else than technology development, the same techniques can also be served for the purposes of process window optimization and tool/ recipe/ process monitoring/qualification applications in volume production.
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Ming-Ta Lei, Kok-Hiang Tang, Yung-Chih Wang, Chia-Hsing Huang, Chih-Cherng Jeng, Lu-Kai Wang, Wei Fang, Yan Zhao, Jack Jau, Chin C. Hsia, and M. S. Liang "In-line semi-electrical process diagnosis methodology for integrated process window optimization of 65nm and below technology nodes", Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61521T (24 March 2006); https://doi.org/10.1117/12.657803
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