Paper
24 March 2006 AIM technology for nonvolatile memories microelectronics devices
Pier Luigi Rigolli, Laura Rozzoni, Catia Turco, Umberto Iessi, Marco Polli, Elyakim Kassel, Pavel Izikson, Yosef Avrahamov
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Abstract
Accurate and precise overlay metrology is a critical requirement in order to achieve high product yield in microelectronic manufacturing. Meeting the tighter overlay measurement error requirements for 90nm technology and beyond is a dramatic challenge for optical metrology techniques using only conventional overlay marks like Bar in Bar (BiB) or Frame in Frames (FiF). New deficiencies, affecting traditional overlay marks, become evident as microlithography processes are developed for each new design rule node. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. In this paper we will review the superior performances of grating-based AIM marks to provide a complete solution to control lithography overlay errors for new generation devices. Examples of successful application of AIM technology to FEOL and Cu-BEOL process steps of advanced non volatile memory devices manufacturing are illustrated. An additional advantage of the adoption of AIM marks is that the significant reduction of target noise versus conventional marks revealed systematic differences within the lithography cluster which were previously obscure offering a new tool to optimize litho cells. In this paper we demonstrated that AIM target architecture enables high performance metrology with design rule segmented targets - a prerequisite to have overlay marks fully compatible with design rule sensitive process steps.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Pier Luigi Rigolli, Laura Rozzoni, Catia Turco, Umberto Iessi, Marco Polli, Elyakim Kassel, Pavel Izikson, and Yosef Avrahamov "AIM technology for nonvolatile memories microelectronics devices", Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61524C (24 March 2006); https://doi.org/10.1117/12.656485
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Cited by 6 scholarly publications.
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KEYWORDS
Overlay metrology

Metrology

Image segmentation

Front end of line

Semiconducting wafers

Chemical mechanical planarization

Metals

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