11 April 2006 Design and development of next-generation bottom anti-reflective coatings for 45nm process with hyper NA lithography
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Proceedings Volume 6153, Advances in Resist Technology and Processing XXIII; 61532L (2006); doi: 10.1117/12.656132
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States
Abstract
Integrated circuit manufacturers are consistently seeking to minimize device feature dimensions in order to reduce chip size and increase integration level. Feature sizes on chips are achieved sub 65nm with the advanced 193nm microlithography process. R&D activities of 45nm process have been started so far, and 193nm lithography is used for this technology. The key parameters for this lithography process are NA of exposure tool, resolution capability of resist, and reflectivity control with bottom anti-reflective coating (BARC). In the point of etching process, single-layer resist process can't be applied because resist thickness is too thin for getting suitable aspect ratio. Therefore, it is necessary to design novel BARC system and develop hard mask materials having high etching selectivity. This system and these materials can be used for 45nm generation lithography. Nissan Chemical Industries, Ltd. and Brewer Science, Inc. have been designed and developed the advanced BARCs for the above propose. In order to satisfy our target, we have developed novel BARC and hard mask materials. We investigated the multi-layer resist process stacked 4 layers (resist / thin BARC / silicon-contained BARC (Si-ARC) / spin on carbon hard mask (SOC)) (4 layers process). 4 layers process showed the excellent lithographic performance and pattern transfer performance. In this paper, we will discuss the detail of our approach and materials for 4 layers process.
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Makoto Nakajima, Takahiro Sakaguchi, Keisuke Hashimoto, Rikimaru Sakamoto, Takahiro Kishioka, Satoshi Takei, Tomoyuki Enomoto, Yasuyuki Nakajima, "Design and development of next-generation bottom anti-reflective coatings for 45nm process with hyper NA lithography", Proc. SPIE 6153, Advances in Resist Technology and Processing XXIII, 61532L (11 April 2006); doi: 10.1117/12.656132; https://doi.org/10.1117/12.656132
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KEYWORDS
System on a chip

Etching

Photoresist processing

Lithography

Photomasks

Silicon

Semiconducting wafers

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