The widespread adoption of advanced packaging techniques is driven by electrical device performance and chip form factor considerations. Flipchip packaging is currently growing at a 25% compound annual rate and it is expected that 90% of all 65 nm logic devices will be bumped. To ensure optimal productivity and cost of ownership, it is imperative to employ lithographic materials that are optimized for these applications and that meet all device specifications.
Bump processing typically has one or more levels that require a permanent layer either to relieve stress on the die (stress buffer layer) or to redistribute electrical connections (redistribution layer). Since these layers remain on the wafer, the mechanical and electrical properties of the material are as important as the lithographic properties. This study will characterize a novel negative, siloxane (Shin-Etsu SINR(R)) photoresist for the redistribution and stress buffer application on 300 mm wafers. Siloxanes are a good choice for redistribution and stress buffer layers because of their excellent physical properties, ease of processing and relatively low cure temperatures. The lithographic performance of the SINR is optimized using a broad band, low numerical aperture, 1X stepper. This study evaluates softbake, post exposure bake (PEB), develop conditions and exposure optimization. Due to decreasing feature size at the redistribution level, it is critical to demonstrate CD uniformity and resolution across the entire 300 mm wafer surface. While the CD uniformity data is collected on 300 mm wafers, all process optimization results will be applicable for all standard wafer sizes. The physical properties of the SINR material are evaluated through curing temperature studies and sputtering tests.