The past decade has experienced a remarkable synergy between Resolution Enhancement Technologies (RET) in Optical Lithography and Optical Proximity Correction (OPC). This heterogeneous array of patterning solutions ranges from simple rule-based to more sophisticated model-based corrections, including sub-resolution assist features, partially transmitting masks and various dual mask approaches. A survey of the evolutionary development from the early introduction of the first OPC engines in 1996 to the debut of Immersion Lithography in 2006 reveals that the convergence of RET and OPC has also enabled a progressive selection and fine-tuning of Geometric Design Rules (GDR) at each technology node, based on systematic adoption of lithographic verification. This paper describes the use of "full-chip" lithography verification engines in current Design For Manufacturing (DFM) practices and extends the analysis to identify a set of key technologies and applications for the 45, 32 and 22 nm nodes. As OPC-derived tools enter the stage of maturity, from a software standpoint, their use-model is being greatly broadened from the back-end mask tape-out flow, upstream, directly integrated into physical design verification. Lithography awareness into the physical design environment, mediated by new DFM verification tools and flows, is driving various forms of manufacturable physical layout implementation: from Restricted Design Rules and Flexible Design Rules to Regular Circuit Fabrics. As new lithography solutions, such as immersion lithography and EUV, will have to be deployed within a complex technology framework, the paper also examines the trend towards "layout design regularization" and its implications for patterning and next generation lithographies.