The quality of model-based OPC (MBOPC) depends on both modeling and correction accuracy. As the k1 process factor decreases and design complexity increases, the correction accuracy becomes more important. Especially, in case of high NA immersion lithography with strong off-axis illumination (OAI) such as dipole and cross-pole illumination, mask error enhancement factor (MEEF) and normalized intensity log-slope (NILS) vary seriously according to the pattern directions and shapes, so that the normal correction method, which uses the constant damping value, causes the divergence of correction and can hardly define optimum bias. Therefore, we developed design rule (D/R) constraints and new correction method to prevent the divergence and to reduce the OPC run time for sub-60nm device.
In this paper, D/R constraints derived from MEEF are introduced to reduce MEEF across the full chip. In addition, we propose new methods to achieve the global OPC convergence of low-k1 lithography by MEEF-based correction combined with proportion-integral-derivative (PID) controller. The PID controller can prevent the divergence because it considers the derivative term between EPEs (edge placement error) of previous and current iteration. Since MEEF-based correction uses the variable damping value derived from MEEF of each pattern fragment, it is effective for the convergence of the memory bit-line layer composed of the complicated 2D patterns. MEEF-based correction combined with PID controller merges the merits of each method and is found to be a stable correction method for k1 factor smaller than 0.27. Applying the proposed method, we could remove the process weak points having more than 20% CD variation caused by the divergence and achieve sufficient process margin for sub-60nm memory device. OPC run time is also reduced by 40% compared with the normal correction method.