15 March 2006 Finding the right way: DFM versus area efficiency for 65 nm gate layer lithography
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Abstract
DFM (Design for Manufacturing) has become a buzzword for lithography since the 90nm node. Implementing DFM intelligently can boost yield rates and reliability in semiconductor manufacturing significantly. However, any restriction on the design space will always result in an area loss, thus diminishing the effective shrink factor for a given technology. For a lithographer, the key task is to develop a manufacturable process, while not sacrificing too much area. We have developed a high performing lithography process for attenuated gate level lithography that is based on aggressive illumination and a newly optimized SRAF placement schemes. In this paper we present our methodology and results for this optimization, using an anchored simulation model. The wafer results largely confirm the predictions of the simulations. The use of aggressive SRAF (Sub Resolution Assist Features) strategy leads to reduction of forbidden pitch regions without any SRAF printing. The data show that our OPC is capable of correcting the PC tip to tip distance without bridging between the tips in dense SRAM cells. SRAF strategy for various 2D cases has also been verified on wafer. We have shown that aggressive illumination schemes yielding a high performing lithography process can be employed without sacrificing area. By carefully choosing processing conditions, we were able develop a process that has very little restrictions for design. In our approach, the remaining issues can be addressed by DFM, partly in data prep procedures, which are largely area neutral and transparent to the designers. Hence, we have shown successfully, that DFM and effective technology shrinks are not mutually exclusive.
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Chandra S. Sarma, Chandra S. Sarma, Steven Scheer, Steven Scheer, Klaus Herold, Klaus Herold, Carlos Fonseca, Carlos Fonseca, Alan Thomas, Alan Thomas, Uwe Paul Schroeder, Uwe Paul Schroeder, } "Finding the right way: DFM versus area efficiency for 65 nm gate layer lithography", Proc. SPIE 6154, Optical Microlithography XIX, 61541L (15 March 2006); doi: 10.1117/12.656633; https://doi.org/10.1117/12.656633
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