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15 March 2006 Pushing the lithography limit: applying inverse lithography technology (ILT) at the 65nm generation
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Abstract
This paper presents the results of applying ILT to SMIC's first 65nm tape out. ILT mathematically determines the mask features that produce the desired on-wafer results for best pattern fidelity, largest process window or an desired combination of both. SMIC applied this technology to its first 65nm tape-out to study its performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first set of test cases, because SRAM bit-cells contain features which are lithographically challenging. Firstly, three experiments were performed to optimize the illumination and mask design of a pair of layers by optimizing exposure energy, enabling SRAF, and enforcing mask constraints. Secondly, mask manufacturability (including fracturing and writing time) and wafer print performance of ILT was studied. Thirdly, mask patterns generated by both conventional Optical Proximity Correction (OPC) and ILT, both using only their optical models, were placed on the mask side-by-side. The results demonstrated that ILT achieved better CD accuracy and produced significantly larger process window than conventional OPC.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chi-Yuan Hung, Bin Zhang, Eric Guo, Linyong Pang, Yong Liu, Kechang Wang, and Grace Dai "Pushing the lithography limit: applying inverse lithography technology (ILT) at the 65nm generation", Proc. SPIE 6154, Optical Microlithography XIX, 61541M (15 March 2006); https://doi.org/10.1117/12.655728
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