Model-Based OPC has become a standard practice and centerpiece for 130nm technology node and below. And every model builder is trying to setup a physically realistic model that is adequately calibrated contains the information which can be used for process predictions and analysis of a given process. But there still are some unknown/not-well-understood physics in the process such as line edge roughness (LER). The LER is one of the most worrisome non-tool-related obstacles faced by next-generation lithography. Nowadays, considerable effort is devoted to moderating its effects, as well as understanding its impact on devices. It is a persistent problem for 193 nm micro-lithography and will carry us for at least three generations, culminating with immersion lithography. Some studies showed LER has several sources and forms. It can be quantified by an LER measurement with a top-down CD measurement. However, there are other ways in which LER shows up, such as line breakage results from insufficient resist or mask patterning processes, line-width aspect ratio or just topography. Here we collected huge amount of line-width ADI CD datasets together with LER for each edge. And try to show even using the average value of different datasets will take the inaccuracy of measurement into the modeling fitting process, which makes the fitting process more time consuming and might cause losing convergence and stableness. This work is to weight different wafer data points with a weighting function. The weighting function is dependent on the LER value for each One-dimension feature in the sampling space of the modeling fitting. By this approach, we can filter wrong information of the process and make the OPC model more accurate. Further more, we will introduce this factor (LER) into variable threshold modeling parameters and see its differentiations between other Variable Threshold model forms.