Using reconfigurable OPC to improve quality and throughput of sub-100nm IC manufacturing

Richard D. Morse; Pat LoPresti; Kevin Corbett

doi:10.1117/12.656708

20 March 2006 Using reconfigurable OPC to improve quality and throughput of sub-100nm IC manufacturing

Richard D. Morse, Pat LoPresti, Kevin Corbett

Proceedings Volume 6154, Optical Microlithography XIX; 61543D (2006) https://doi.org/10.1117/12.656708
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

In this paper we propose an alternative sub-100nm manufacturing flow using reconfigurable OPC technology. In this flow, an initial full-chip OPC is performed similar to the conventional approach. But when errors are found during verification - which can include checks across the process window - we optimize the OPC results locally with reconfigurable OPC technology without disturbing the OPC results elsewhere in the design. Creating optimized local solutions for LRC errors offers a more manufacturable solution, and it virtually guarantees rapid and correct OPC convergence. These chip-specific solutions can then be retained for future runs and the results analyzed for inclusion in the global or "master" recipe.

Citation Download Citation

Richard D. Morse, Pat LoPresti, and Kevin Corbett "Using reconfigurable OPC to improve quality and throughput of sub-100nm IC manufacturing", Proc. SPIE 6154, Optical Microlithography XIX, 61543D (20 March 2006); https://doi.org/10.1117/12.656708

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