15 March 2006 Spatial modeling of micron-scale gate length variation
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Abstract
Systematic gate length variations caused by microlithographic processing [1] have a significant impact on the variability of circuit performance. In this work, rigorous simulation shows the importance of proper spatial modeling. More specifically, the Monte Carlo framework used in [2] has been recast into an analytical macromodel-based Matlab framework. With accuracy in the 2% range, this analytical model allows for much faster critical path variability analysis. The analytical framework has been used to evaluate the assumptions made about the structure of spatial variation in [2]. It has been shown that a more rigorously-defined nested variance model of spatial variation yields substantially different circuit performance variability results. To further establish the nature of spatial variation in the sub-mm regime, a new set of electrical linewidth metrology (ELM) test structures is proposed. These ELM structures enable the measurement of critical dimensions of neighboring polysilicon lines packed at maximum density. Dummy lines may also be inserted between the measurable polysilicon lines, allowing for measurement of near-neighbor lines and thereby increasing the total measurable range. With the fine granularity and wide range of these test structures, spatial variation and correlation in the separation range of 0.2μm to 1.0mm can be measured.
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Paul Friedberg, Paul Friedberg, Willy Cheung, Willy Cheung, Costas J. Spanos, Costas J. Spanos, } "Spatial modeling of micron-scale gate length variation", Proc. SPIE 6155, Data Analysis and Modeling for Process Control III, 61550C (15 March 2006); doi: 10.1117/12.656521; https://doi.org/10.1117/12.656521
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