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Call for an industry standard for pattern transfer models for usage in OPC and design for manufacturability
Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation
DFM: a practical layout optimization procedure for the improved process window for an existing 90-nm product
Across field CD control improvement for critical level imaging: new applications for layout correction and optimization
A high aspect ratio Si-fin FinFET fabricated with 193nm scanner photolithography and thermal oxide hard mask etching techniques
Accurate OPC model generation through use of a streamlined data flow incorporating automated test-structure layout and CD-SEM recipe generation
The use of optical proximity correction to compensate for reflectivity differences in N type and P type poly-silicon