24 March 2006 Development of hot spot fixer (HSF)
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Abstract
A new design for manufacturability (DfM) scheme with a lithography compliance check (LCC) and hot spot fixing (HSF) flow has been developed to guarantee design compliance for OPC and RET by combining lithography simulator, hot spot detector and layout modification tool. Hot spots highlighted by the LCC flow are removed by the HSF flow following modification rule consists of "Line-Sizing" (LS) and "Space-Sizing (SS)" that are resize value of line-width and space-width for the original pattern. In order to meet layout modification requirements at the pre- and post- tape out (T.O.) stages, the priorities individually set for the modification rules and the design rules, which provides flexibly to achieve the modification scheme desirable at each stage. For handling large data at a fast speed, Layout Analyzer (LA) and Layout Optimizer (LO) engines were combined with the HSF flow. LA is used to reconstruct the original hierarchy structure, clips off small parts of the layout that include hot spots from the original layout and sends those to LO in order to reduce the computational time and resource. LO optimizes the clipped off layout following the prioritized modification- and design-rules. The new DfM scheme was found to be quite effective for hot spot cleaning for 65nm node and beyond, since it was demonstrated that the HSF flow improved the lithography margin for the metal layer of 65nm node full-chip data by reducing number of hot spots to below 0.1% of original within about 12 hours, using 1CPU of commercially available workstation.
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Toshiya Kotani, Toshiya Kotani, Suigen Kyoh, Suigen Kyoh, Sachiko Kobayashi, Sachiko Kobayashi, Takatoshi Inazu, Takatoshi Inazu, Atsuhiko Ikeuchi, Atsuhiko Ikeuchi, Yukihiro Urakawa, Yukihiro Urakawa, Soichi Inoue, Soichi Inoue, Etsuya Morita, Etsuya Morita, Simon Klaver, Simon Klaver, Takumi Horiuchi, Takumi Horiuchi, Johan Peeters, Johan Peeters, Satoshi Kuramoto, Satoshi Kuramoto, } "Development of hot spot fixer (HSF)", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560H (24 March 2006); doi: 10.1117/12.657806; https://doi.org/10.1117/12.657806
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