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14 March 2006 Across field CD control improvement for critical level imaging: new applications for layout correction and optimization
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As minimum groundrules for chipmanufacturing continue to shrink the lithography process is pushed further and further into the low k1 domain. One of the key characteristics of low k1 lithography is the fact that process variations are increasingly more difficult to manage and the resulting CD variations are significant relative to the nominal dimensions. As a result it is quite common for process engineers to define process budgets, mostly dose and focus budgets. These budgets summarize the effects of various exposure and process contributors and provide the range within which the process is expected to fluctuate. An important task of process design is to ensure that within these budgets no catastrophic patterning failures occur, but even more importantly that the CD variations remain within the allowed design tolerances. Various techniques have been developed to reduce the sensitivity of the lithography process to process variations, among those one of the more prominent and quite widely adopted techniques are subresolution enhancements. Traditionally subresolution assist features are placed in the design using rules based approaches. This work presents a model based approach to assist feature placement. In this approach assist features are placed such that the resulting mask exhibits the minimum sensitivity to the specific process variations encountered. The type of process variation may be defined by the user as serious of worst case conditions, for example in dose and focus. The technique however is general enough to allow a variety of process variations to be included. This work focuses on demonstrating the key concept and show it's validity. The approach demonstrated in this work is fully integrated with the process budget concept and therefore allows a "process aware" mask optimization.
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Franz Zach, Gökhan Percin, and Apo Sezginer "Across field CD control improvement for critical level imaging: new applications for layout correction and optimization", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560I (14 March 2006);

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