14 March 2006 Meeting critical gate linewidth control needs at the 65 nm node
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Abstract
With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications. This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our team's success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Arpan Mahorowala, Arpan Mahorowala, Scott Halle, Scott Halle, Allen Gabor, Allen Gabor, William Chu, William Chu, Alexandra Barberet, Alexandra Barberet, Donald Samuels, Donald Samuels, Amr Abdo, Amr Abdo, Len Tsou, Len Tsou, Wendy Yan, Wendy Yan, Seiji Iseda, Seiji Iseda, Kaushal Patel, Kaushal Patel, Bachir Dirahoui, Bachir Dirahoui, Asuka Nomura, Asuka Nomura, Ishtiaq Ahsan, Ishtiaq Ahsan, Faisal Azam, Faisal Azam, Gary Berg, Gary Berg, Andrew Brendler, Andrew Brendler, Jeffrey Zimmerman, Jeffrey Zimmerman, Tom Faure, Tom Faure, } "Meeting critical gate linewidth control needs at the 65 nm node", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560M (14 March 2006); doi: 10.1117/12.659427; https://doi.org/10.1117/12.659427
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