Translator Disclaimer
Paper
14 March 2006 Impact of process variation on 65nm across-chip linewidth variation
Author Affiliations +
Abstract
The latest improvements in process-aware lithography modeling have resulted in improved simulation accuracy through the dose and focus process window. This coupled with the advancements in high speed, full chip grid-based simulation provide a powerful combination for accurate process window simulation. At the 65nm node, gate CD control becomes ever more critical so understanding the amount of CD variation through the full process window is crucial. This paper will use the aforementioned simulation capability to assess the impact of process variation on ACLV (Across-Chip Linewidth Variation) and critical failures at the 65nm node. The impact of focus, exposure, and misalignment errors in manufacturing is explored to quantify both CD control and catastrophic printing failure. It is shown that there is good correlation between predicted and experimental results.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Le Hong, Travis Brist, Pat LaCour, John Sturtevant, Martin Niehoff, and Philipp Niedermaier "Impact of process variation on 65nm across-chip linewidth variation", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560Q (14 March 2006); https://doi.org/10.1117/12.660541
PROCEEDINGS
9 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT

Dense OPC for 65nm and below
Proceedings of SPIE (November 09 2005)
Programmable RET mask layout verification
Proceedings of SPIE (December 27 2002)
Improved manufacturability by OPC based on defocus data
Proceedings of SPIE (July 10 2003)
Automatic OPC mask shape repair
Proceedings of SPIE (March 21 2007)
Taming pattern and focus variation in VLSI design
Proceedings of SPIE (May 03 2004)

Back to Top