14 March 2006 Considerations of model-based OPC verification for sub-70nm memory device
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Abstract
As the minimum feature size of memory devices are getting smaller, model-based OPC accuracy requirements call for highly accurate process modeling and modeling strategies. Therefore, model-based OPC verification process required high accuracy due to unexpected errors on low-k process scheme. Model of model-based OPC verification (MBV) process has to be accurate in order to detect potential hot spot and human errors, which includes physical design rule violation, mask fabrication rule violation and DB handling errors, and has also suitable speed of fast feedback to OPC and design side in view of DFM. Recently, model-based OPC tools have progressively advanced in term of modeling. Nevertheless, because we applied extreme off-axis illumination on sub-70nm gate levels, model can not exactly predict the wafer results and have low accuracy. In this paper, we evaluated several commercial model-based OPC verification (MBV) tools for sub 70nm memory device and compare review results with real wafer results. With the results, we analyze and discuss the major factor for poor OPC and MBV model accuracy for low-k process. Also we will be discussing about suitable speed of feedback to OPC and design part in terms of methods for analysis and categorization of huge number of errors. We are focus on these two goals for MBV and discuss major factors for consideration. Finally, we would like to suggest optimized procedure for OPC verification by using calibrated models on sub-70nm memory Device.
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Cheol-Kyun Kim, Jae-Seung Choi, Byung-Ho Nam, DongGyu Yim, "Considerations of model-based OPC verification for sub-70nm memory device", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61561D (14 March 2006); doi: 10.1117/12.656852; https://doi.org/10.1117/12.656852
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