14 March 2006 RET for the wiring layer of a 3D memory
Author Affiliations +
Abstract
A typical wiring layer of SanDisk 3-dimensional memory device includes a dense array of lines. Every other line terminates in an enlarged contact pad at the edge of the array. The pitch of the pads is twice the pitch of the dense array. When process conditions are optimized for the dense array, the gap between the pads becomes a weak point. The gap has a smaller depth of focus. As defocus increases, the space between the pads diminishes and bridges. We present a method of significantly increasing the depth of focus of the pads at the end of the dense array. By placing sub-resolution cutouts in the pads, we equalize the dominant pitch of the pads and the dense array.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yung-Tin Chen, Yung-Tin Chen, Paul Poon, Paul Poon, Chris Petti, Chris Petti, Vishnu Kamat, Vishnu Kamat, Apo Sezginer, Apo Sezginer, Hsu-Ting Huang, Hsu-Ting Huang, } "RET for the wiring layer of a 3D memory", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61561E (14 March 2006); doi: 10.1117/12.656725; https://doi.org/10.1117/12.656725
PROCEEDINGS
8 PAGES


SHARE
Back to Top