To continue with the development of a wireless sensing unit built upon an off-the-shelf FPGA development board presented by the authors at SPIE 2005, this paper outlines a further effort consisting of embedding onboard computations, simulation and validation of the FPGA-based wireless sensing unit that is able to collect, process and transmit data. This research supports the concepts of decentralized wireless sensor networks and local-based damage detection, where individual wireless sensor nodes are capable of performing intricate tasks and can eventually transmit the processed results. An FPGA-based hardware platform is thus looked upon as a major contender for performing this function in a proficient manner. Throughout this research, the principal design complexities, in terms of both hardware and software development, are kept to a minimum. Development cycle and monetary cost of the hardware are other major considerations for this research. Data processing functions including windowing, Fast Fourier Transform (FFT), peak detection, are implemented into the selected FPGA, when limitations of different design options are explored to yield a solution that optimizes the resources of the selected FPGA. Numerical simulations and laboratory validations are carried out to scrutinize the operations and flexibility of the design.