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18 April 2006 On-board SRAM signal density stress prediction
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Proceedings Volume 6205, Thermosense XXVIII; 62050R (2006)
Event: Defense and Security Symposium, 2006, Orlando (Kissimmee), Florida, United States
Static Random Access Memory (SRAM) chips undergo several types of stress in the field. Existing work has concentrated primarily on humidity and thermal stress; there has been relatively little emphasis on signal density stress prediction. Objectives of this study were to (1) explore the impact of signal density stress on SRAM functionality, (2) observe thermal profile differences under signal density stress over time, (3) predict stress levels using artificial neural network models, and (4) develop a generic methodology for signal density stress prediction. An 8051 programming board containing an SRAM chip was used. Two kinds of signal density stress were investigated - varying the content written to memory, and varying signal frequency in accessing SRAM through flash memory. Preliminary experiments suggest that both types of stress impact the SRAM thermal profile. Thermal profile data were used to build back propagation neural network models; 70% of the data was used to build the models and 30% was used for testing. Various neural network training functions and topologies were used to predict chip stress level given thermal profile data. Data from both the die area and the entire chip were used. For both types of stress, using data from the die area in a network with a 3-3-1 topology yielded the lowest average error rate - 1.3% for data content stress level prediction and 7.6 % for signal frequency stress level prediction. The trainRP function resulted in a lower error rate than other training functions that were evaluated.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sheng-Jen Hsieh and Kartik Sharma "On-board SRAM signal density stress prediction", Proc. SPIE 6205, Thermosense XXVIII, 62050R (18 April 2006);

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