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20 May 2006 EUV mask process development and integration
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Proceedings Volume 6283, Photomask and Next-Generation Lithography Mask Technology XIII; 62830G (2006)
Event: Photomask and Next Generation Lithography Mask Technology XIII, 2006, Yokohama, Japan
It becomes increasingly important to have an integrated process for Extreme UltraViolet (EUV) mask fabrication in order to meet all the requirements for the 32 nm technology node and beyond. Intel Corporation established the EUV mask pilot line by introducing EUV-specific tool sets while capitalizing on the existing photomask technology and utilizing the standard photomask equipment and processes in 2004. Since then, significant progress has been made in many areas including absorber film deposition, mask patterning optimization, mask blank and patterned mask defect inspection, pattern defect repair, and EUV mask reflectivity metrology. In this paper we will present the EUV mask process with the integrated solution and the results of the mask patterning process, Ta-based in-house absorber film deposition, absorber dry etch optimization, EUV mask pattern defect inspection, absorber defect repair, and mask reflectivity performance. The EUV resist wafer print using the test masks that are fabricated in the EUV mask pilot line will be discussed as well.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Guojing Zhang, Pei-Yang Yan, Ted Liang, Yan Du, Peter Sanchez, Seh-jin Park, Eric J. Lanzendorf, Chang Ju Choi, Emily Y. Shu, Alan R. Stivers, Jeff Farnsworth, Kangmin Hsia, Manish Chandhok, Michael J. Leeson, and Gilroy Vandentop "EUV mask process development and integration", Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 62830G (20 May 2006);


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