At deep sub-wavelength nodes, it is difficult to transfer accurate mask pattern onto the wafer. However, actual gate pattern is distorted, and timing analysis tools calculates circuit performance on the assumption that the same gate length exists throughout the whole gate width. We calculated the property of the original 2 dimensional distorted transistor by using distribution of gate length. Firstly, in order to evaluate the accuracy of this approach, we have compared them with experimental results that may influence the 65 nm-node design rule. In the conventional method using a rectangular model, results of transistor properties are different from the experimental values, however, results of this approach can reproduce the experimental results. Secondly, this approach is applied to optimization of layout design and OPC. In order to investigate the influence of circuit performance on a layout design and OPC, we calculated the properties (drive current; Ion and leakage current; Ioff) of each transistor contained in standard cell library which is most referred to in a system LSI. We have investigated 2 layouts and 8 OPCs. According to these results, we find out that optimal OPC differs according to the prioritization of Ion and Ioff, whether it is an N-channel or P-channel, and also by layout. Furthermore relaxation of layout decreases variability of Ion caused by defocus. Moreover, since the influence of pattern distortion can be expressed by circuit term such as Ion and Ioff in addition to conventional process terms, it becomes easier for designers to understand manufacturing issues.