We have reported a new paradigm in design database inspection, moving the OPC verification from the design plane to the wafer plane where it really matters. The DesignScanTM system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window for an entire chip design. The simulated images are compared to the best focus/exposure reference, and defect detection and CD variation and uniformity algorithms are applied to determine if any unacceptable variation in the pattern occurs within the nominal process window. In addition, DesignScan can sort out detected defects based on the severity of defects-their impact to lithography process window. Such sorting provides powerful guide for prioritizing defective patterns for fixing based upon their contribution for process window enlargement.
In this paper, we will report on inspection results of DesignScan on a ProMOS test device database with two different OPC models, in particular its ability to sort defects based on their process window impact. The process window can be enlarged by fixing the weakest patterns, which are the limiting patterns of the process window, until the next weakest patterns become the limiting ones. Previously, we have demonstrated conceptually a database design error detection and correction using DesignScan and Aprio's reconfigurable OPC technology on a test database through programmed defects. We will demonstrate in this paper the process window enhancements achieved on a customer test database through the fixing of process window limiting patterns using integrated defect detection, defect severity sorting and OPC correction for the first few groups of defects.