20 May 2006 A single-exposure approach for patterning 45nm flash/DRAM contact hole mask
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Proceedings Volume 6283, Photomask and Next-Generation Lithography Mask Technology XIII; 62831A (2006); doi: 10.1117/12.681873
Event: Photomask and Next Generation Lithography Mask Technology XIII, 2006, Yokohama, Japan
Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k1 conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k1<0.31, both resolution and imaging contrast can become severely limited at NA<0.85 with some commonly available off-axis illumination sources. Hyper-NA and immersion lithography with polarized illumination capability can significantly increase the process latitude and is indispensable for manufacturing at sub-50nm design rule and beyond. In this work, we describe our single-exposure approach for patterning Flash/DRAM contact-hole patterns with 120nm minimum pitch (and 60nm CH target CD). We use 6% attPSM dark-field mask both in simulations and for wafer exposures on ASML XT:1700i at NA=1.2. We begin with illumination source optimization using full vector high-NA simulation with (unpolarized and Y polarized illumination) a production resist stack and taking into account during the optimization all manufacturability requirements for the corresponding diffractive optical element (DOE) that produces the optimized source at the mask level. Using the optimized source, model-based OPC treatment was performed, which includes scattering bars (SB) placement using IMLTM technology and model-based CH feature biasing (MOPC) to achieve the optimum pattern printing fidelity in-focus and process latitude. To further increase of the depth of focus (DOF) for common process window (CPW) from 150nm to >250m, we used the focus scan (or, focus drilling) technique which is available in today's leading 193nm scanners. Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA>1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF ~100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased >25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging, we show that the worst-case individual DOF can be easily doubled (from 150nm to >300nm) and EL at best focus (BF) remains >10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ting Chen, Doug Van Den Broeke, Edita Tejnil, Stephen Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep De Vocht, Noel Corcoran, J. Fung Chen, Eddy van der Heijden, Jo Finders, Andre Engelen, Robert Socha, "A single-exposure approach for patterning 45nm flash/DRAM contact hole mask", Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 62831A (20 May 2006); doi: 10.1117/12.681873; https://doi.org/10.1117/12.681873


Optical proximity correction

Optical lithography



Lithographic illumination

Semiconducting wafers


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