20 May 2006 Simultaneous layout, process, and model optimization within an integrated design-for-yield environment
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Proceedings Volume 6283, Photomask and Next-Generation Lithography Mask Technology XIII; 62832S (2006) https://doi.org/10.1117/12.681806
Event: Photomask and Next Generation Lithography Mask Technology XIII, 2006, Yokohama, Japan
Abstract
Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability concerns. This requires very accurate models to analyze the manufacturability issues. This also often requires simultaneous analysis and optimization of both layout and the process. Most advanced layout patterns are extremely hard to manufacture and consequently run into the risk of re-spins. Therefore, an early pre-tapeout analysis and troubleshooting of various layout, process, and RET issues has become a very important task. Our paper gives examples of how these and other related issues can be addressed using a commercially available Design-for-Yield integrated environment.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dmitri Lapanik, Dmitri Lapanik, Lynn Cai, Lynn Cai, Chung-Shin Kang, Chung-Shin Kang, Bob Naber, Bob Naber, Jason Sweis, Jason Sweis, Wolf Staud, Wolf Staud, } "Simultaneous layout, process, and model optimization within an integrated design-for-yield environment", Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 62832S (20 May 2006); doi: 10.1117/12.681806; https://doi.org/10.1117/12.681806
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