25 August 2006 Faster and smaller hardware implementation of XTR
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Modular multiplication is the core of most Public Key Cryptosystems and therefore its implementation plays a crucial role in the overall efficiency of asymmetric cryptosystems. Hardware approaches provide advantages over software in the framework of efficient dedicated accelerators. The concerns of the designers are mainly the die size, frequency, latency (throughput) and power consumption of those solutions. We show in this paper how Booth recoding, pipelining, Montgomery modular multiplication and carry save adders offer an attractive solution for hardware modular multiplication. Although most of the hereafter techniques stand as state-of-the-art, the combination described here is unique and particularly efficient in the context of constrained hardware design of XTR cryptosystem. Our solution is implemented on an FPGA platform and compared with previous results. The area-time ratio is improved by around a factor of 3.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Neve, Eric Peeters, Guerric Meurice de Dormale, Jean-Jacques Quisquater, "Faster and smaller hardware implementation of XTR", Proc. SPIE 6313, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI, 631309 (25 August 2006); doi: 10.1117/12.680441; https://doi.org/10.1117/12.680441


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