Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top critical issues. A survey was created with support from SEMATECH and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of semiconductor company mask technologists, merchant mask suppliers, and industry equipment makers. This year's assessment is the fifth in the current series of annual reports. With continued industry support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey is basically the same as the 2005 survey. Questions are grouped into categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns and Services, Operating Cost Factors, and Equipment Utilization. Within each category is a multitude of questions that create a detailed profile of both the business and technical status of the critical mask industry.

This paper is a revision of the authors' previous work entitled "Experimental characterization of the receding meniscus under conditions associated with immersion lithography," presented in Optical Microlithography XIX, edited by Donis G. Flagello, Proceedings of SPIE Vol. 6154 (SPIE, Bellingham, WA, 2006) 61540R. Several engineering challenges accompany the insertion of the immersion fluid in a production tool, one of the most important being the confinement of a relatively small amount of liquid to the under-lens region. The semiconductor industry demands high throughput, leading to relatively large wafer scan velocities and accelerations. These result in large viscous and inertial forces on the three-phase contact line between the liquid, air, and substrate. If the fluid dynamic forces exceed the resisting surface tension force then residual liquid is deposited onto the substrate that has passed beneath the lens. Liquid deposition is undesirable; as the droplets evaporate they will deposit impurities on the substrate. In an immersion lithography tool, these impurities may be transmitted to the printed pattern as defects. A substantial effort was undertaken relative to the experimental investigation of the static and dynamic contact angle under conditions that are consistent with immersion lithography. A semi-empirical model is described here in order to predict the velocity at which liquid loss occurs. This model is based on fluid physics and correlated to measurements of the dynamic and static contact angles. The model describes two regimes, an inertial and a capillary regime, that are characterized by two distinct liquid loss processes. The semi-empirical model provides the semiconductor industry with a useful predictive tool for reducing defects associated with film pulling.

As critical dimension uniformity requirements tighten for advanced technology nodes, it becomes increasingly important to characterize and correct for systematic sources of critical dimension error in mask manufacturing. A long range proximity effect has been previously reported in the industry to occur in chemically amplified resists that appears to be related to the develop process and we call this phenomenon chemical flare. Several attempts to modulate this effect have been characterized and at least one develop nozzle modification has been found to reduce chemical flare by ~50%. In addition, develop time, develop and rinse processes, and top anti-reflective coatings have been evaluated as methods of minimizing chemical flare effects in e-beam lithography applications. Positive and negative chemically amplified ebeam resists have been evaluated and characterized for this effect.

Chemically amplified resist (CAR) performance can be greatly influenced by post apply bake (PAB) and post exposure bake (PEB) conditions. The difficulty with optimizing these conditions for photomask process is cost and time. In typical wafer CAR resist development, multiple wafer splits and skews can be rapidly processed with relatively low cost and fast turn around time, whereas in photomask processing each ebeam-written mask with a set of DOE conditions can be expensive and time consuming to produce. This paper discusses a novel mask design and testing methodology that allow for many combinations of PEB and PAB conditions to be evaluated with one mask. In brief, this methodology employs orthogonal PAB and PEB thermal gradients across a plate. Some thermal profile, darkloss, resist top down critical dimensions (CD), and SEM cross section image results will be shared and discussed.

An ultra-uniform, ultra-thin resist deposition process is presented. Nanometrix applications development with Ultra Thin Polymer Films (UTPF) production process addresses several problems related to resist deposition for lithographic applications. The linear coating process based on the Schneider-Picard (SP) method is a driven assembly process. Linear meter per minute coating rates are produced while providing an outstanding film quality at nano- to micro scale thinness. Therefore, this coating method provides a viable alternative for resist application. Our present developments on nano and micro ultra-thin polymer film coatings give substantial new solutions for improved, faster and less expensive coating production. Materials, writing and quality control costs may be substantially reduced with UTPF deposition technology. Results from three resists are presented in this paper. E-beam direct writing on 8 nm PMMA and photolithography on ILine and DUV resists in the scale of 30 nm are presented. Thicker resist deposition has been performed as well in the range of 1-10 microns thick. Film edge bead in the order of film thickness are obtained (1000 x smaller than spin coating process). Substrates were all coated with uniform ultra-thin films at a rate of one square meter per minute with atomic smoothness. This technological breakthrough enables a valuable solution for resist deposition and lithography fabrication at the nano and micro scales and provides resist uniformity required for current and future critical dimension specifications.

Studies on pattern transfer of next generation lithographic (EUV) photomask were carried out. Based on current absorber layer material candidates, thermodynamic calculations were performed and plasma etch gas system and composition were investigated. The gas systems have the advantage of all etch products being in volatile condition. This is helpful to keep the etch process and etch chamber clean. For etch CD bias challenge in EUV photomask etch, self-mask concept was investigated, which makes anti-reflective (AR) sub-layer of the absorber layer function as a hard mask for the bulk absorber layer beneath. It significantly reduces etch CD bias and improves pattern transfer fidelity. For common candidates of EUV mask absorber layers such as TaBO/TaBN and TaSiON/TaSi, reactive gas systems were proposed according to thermodynamic calculations with all products volatile. AR sub-layers were etched in one gas composition with volatiles. Once the AR sub-layer is etched through, gas composition was changed so that the bulk absorber sub-layer beneath is etched selectively with volatile products. Excellent results in profiles, CD bias, CD uniformity, and underneath buffer/capping layer impact have been demonstrated.

The ITRS roadmap indicates that significant improvements in photomask processing will be necessary to achieve the design goals of 45nm technology node masks. In the past, etch systems were designed to produce an etch signature that was as "flat" as possible to avoid introducing undesirable signatures in the final product. However, as error budgets are shrinking for all tools in the process line, the signatures produced by etch systems are used to compensate for some of the upstream CD issues. Process modifications have been used successfully in this fashion, but frequently process adjustment alone is not sufficient. CD uniformity results from a complex interaction between the system and the sample. An etch system must be capable of adjusting radial, linear, and loading etch uniformity components to compensate for the specific needs of each sample. The adjustments should also be as independent of process as possible. Towards this end, experiments were conducted with various etch technologies to create specific, controllable etch signatures on demand without the need for hardware changes. CD data collected from binary chrome photomasks was used to verify performance of the uniformity adjustment technologies.

In this study, the method for achieving precise CD MTT (critical dimension mean to target) in manufacturing attenuated PSM (phase shift mask) was investigated. As the specification for photomask becomes tighter, more precise control of CD is required. There are several causes to result in CD MTT error. In general mask patterning processes which are from blank material to dry etch, it is difficult to detect CD MTT error before final CD measurement and correct it. It is necessary to apply new process to mask production to correct CD error and control CD MTT precisely. Reducing number of factors which can have an effect on CD and introducing reliable method to correct CD error are important to achieve accurate CD MTT. For the correction of CD error, the reliability of CD in each measurement step such as resist CD or Cr CD before and after resist removal and effect on items related with CD like CD uniformity, isolated-dense CD difference, etc should be considered and evaluated. In this method to correct CD MTT error, Cr CD after removing resist was measured before MoSiN dry etch and additional corrective Cr dry etch using Cr CD information was applied to cancel CD error and then MoSiN dry etch was followed. In this case, factors affecting final CD are additional corrective Cr etch and MoSiN etch. The relationship between CD shift and corrective Cr etch time for masks with various pattern densities was found and necessary corrective Cr etch time was applied to CD correction process. The CD MTT error is canceled by additional corrective Cr dry etch step. As a result, accurate CD control and significant decrease of CD MTT error for attenuated PSM is achieved through the use of this CD correction method.

Dry etching has become critical to manufacture the resolution enhancement technique (RET) mask in the ArF lithography. Among RET masks, alternating phase shift mask (PSM) and chrome-less phase lithography (CPL) mask require the formation of 180 degrees phase differences by quartz dry etching. There are many error factors, which can influence CD uniformities on mask and wafers, in Quartz dry etch step such as sidewall angle, phase MTT and uniformity, micro-trench, and morphology. Furthermore, quartz depth is hard to control because there is no stopping layer for quartz etching. Additionally, Pattern profile of Chrome layer is very important, because chrome profile affect sidewall angle for quartz. We have simulated and investigated to identify the influences of many error factors on RET. Consequently, we investigated characteristics of quartz dry etching process performance and the influences on resolution, which can be improved by dry etch parameters.

Technology, CAD, and design are increasingly more challenged by Design-for-Manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among multiple design groups and using manual drawing techniques or semi-automated tools with different quality standards. This task becomes even more important for the RF/analog layout where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using standardized, parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, we will show that the standardized layout is the option preferred from the point of view of design, CAD, and technology.

During the last years, various DfM (Design for Manufacturability) concepts have been proposed and discussed. Resolution enhancement technologies with the goal to provide reasonable printability over the whole lithographic process window, and the optimization of these tools and processes by print image simulation (PW-ORC) have become crucial aspects of DfM today. In addition, designers and layouters will become increasingly involved in yield discussions, as they will get tools and methods to identify and remove yield issues in the drawn layout. Such a lithography-aware design data flow, which is called LfD (Litho-friendly Design), is a very important step towards a fully developed DFM environment. Recently, the leading EDA tool vendors have provided tools for efficient process window analysis and a scoring of lithography issues in a form, which is close to productive usability. We report in this paper the implementation of LfD into the design flow of library cells for the 90 nm and the 65 nm design rule technologies. Specific aspects of such a LfD flow, like the availability of robust process models in early development stages are discussed as well as appropriate means to assess the results.

We present a new methodology for a balanced yield-optimization and a new DFM framework which implements it. Our approach allows designers to dynamically balance multiple factors contributing to yield loss and select optimal combination of DFM enhancements based on the current information about the IC layout, the manufacturing process, and known causes of failures. We bring together the information gained from layout analysis, layout-aware circuit analysis, resolution enhancement and optical proximity correction tools, parasitics extraction, timing estimates, and other tools, to suggest the DFM solution which is optimized within the existing constraints on design time and available data. The framework allows us to integrate all available sources of yield information, characterize and compare proposed DFM solutions, quickly adjust them when new data or new analysis tools become available, fine-tune DFM optimization for a particular design and process and provide the IC designer with a customized solution which characterizes the manufacturability of the design, identifies and classifies areas with the most opportunities for improvement, and suggests DFM improvements. The proposed methodology replaces the ad-hoc approach to DFM which targets one yield loss cause at the expense of other factors with a comprehensive analysis of competing DFM techniques and trade-offs between them.

Aggressive line width control requirements for leading edge IC fabrication necessitate integration of novel techniques such as DoseMapper into the lithography process flow. DoseMapper is based on the simple concept that CD uniformity (CDU) can be improved through compensation of CD errors by using the scanner actuators. Specifically, the DoseMapper system allows for compensation of interfield and intrafield CD non-uniformity, based on the spatial distribution of in-line CD measurements or end-of-line electrical parameters for a stable process. This approach is supported by the fact that small variations of linewidth are correlated to exposure dose in a linear fashion. In this work we describe strategies for and results of the application of DoseMapper in a lithographic process for gate layer in a 65nm technology. We will highlight the potential strengths and weaknesses of various DoseMapper strategies to. For instance, we have learned that dose adjustments which are based on post-etch CD signature can lead to degradation of the lithography-based process window especially for 2 -dimensional features due to high MEEF. Therefore, it is asserted that application of DoseMapper in a high-volume manufacturing process requires consideration of such rational tradeoffs as mentioned above. Impact of Mask CD variation on DoseMapper effectiveness will also be discussed. This has the potential to have a significant impact on manufacturability of photo masks for the 65nm node and beyond

As advanced technologies in wafer manufacturing push patterning processes toward lower-k₁ subwavelength printing, lithography for mass production potentially suffers from decreased patterning fidelity. This results in generation of many hotspots, which are actual device patterns with relatively large CD and image errors with respect to on-wafer targets. Hotspots can be formed under a variety of conditions such as the original design being unfriendly to the RET that is applied, unanticipated pattern combinations in rule-based OPC, or inaccuracies in model-based OPC. When these hotspots fall on locations that are critical to the electrical performance of a device, device performance and parametric yield can be significantly degraded. Previous rule-based hotspot detection methods suffer from long runtimes for complicated patterns. Also, the model generation process that captures process variation within simulation-based approaches brings significant overheads in terms of validation, measurement and parameter calibration. In this paper, we first describe a novel detection algorithm for hotspots induced by lithographic uncertainty. Our goal is to rapidly detect all lithographic hotspots without significant accuracy degradation. In other words, we propose a filtering method: as long as there are no "false negatives", i.e., we successfully have a superset of actual hotspots, then our method can dramatically reduce the layout area for golden hotspot analysis. The first step of our hotspot detection algorithm is to build a layout graph which reflects pattern-related CD variation. Given a layout L, the layout graph G = (V, E_c union E_p) consists of nodes V, corner edges E_c and proximity edges E_p. A face in the layout graph includes several close features and the edges between them. Edge weight can be calculated from a traditional 2-D model or a lookup table. We then apply a three-level hotspot detection: (1) edge-level detection finds the hotspot caused by two close features or "L-shaped" features; (2) face-level detection finds the pattern-related hotspots which span several close features; and (3) merged-face-level detection finds hotspots with more complex patterns. To find the merged faces which capture the pattern-related hotspots, we propose to convert the layout into a planar graph G. We then construct its dual graph G^D and sort the dual nodes according to their weights. We merge the sorted dual nodes (i.e., the faces in G) that share a given feature, in sequence. We have tested our flow on several industry testcases. The experimental results show that our method is promising: for a 90nm metal layer with 17 hotspots detected by commercial optical rule check (ORC) tools, our method can detect all of them while the overall runtime improvement is more than 287X.

The mask-making process for 45nm-node and beyond demands higher resolution and CD accuracy. To meet the requirements, the multi-layer resist system is developed as one of the solutions. BIL (Bottom Insulating Layer) can correct the profile of CAR (Chemically Amplified Resist). CAR shows profile degradation by photo-acid loss at the boundary of chrome and resist. The photo-acid loss induces excess footing in positive-tone CAR and under-cutting in negative-tone CAR. BIL reduced the profile degradation to less than half of the conventional resist system. BIL requires no extra mask process steps. Final CD linearity of isolated lines was improved by BIL. It is very beneficial for the patterning of sub-resolution assist features. Moreover, BIL with a hard-mask layer showed superior dry-etching bias performance.

A case study was carried out investigating the influence of different transmission and phase shift materials on lithographic performance at 45 nm node. The bilayer approach for embedded attenuated Phase Shift Masks (EAPSM) offers the advantages to adjust phase shift and transmission independently. The transmission of Ta/SiO2 can be tuned up to 40% depending on the required application. Three different PSM blank types with the stacks Ta/SiO2-6%, Ta/SiO2-30% and Ta/SiON-30% have been manufactured and characterized. Afterwards, an identical line pattern, consisting of different feature sizes and duty cycles, has been patterned in each of the three PSM types as well as in the MoSi-6% for reference. Using the AIMS^TM 45-193i tool we have evaluated the lithographic performance of the four PSM in terms of contrast and process latitude using unpolarized and TE polarized illumination. The case study showed that the process window for Ta/SiO2-6% is comparable to standard MoSi-6%. For dense line application a 6% EAPSM is preferable. The Ta/SiO2-30% EAPSM provides a significantly larger process window for higher duty cycles compared to MoSi-6%. This means a 50% increase in depth of focus (DOF) at 10% exposure latitude (EL). Therefore for logic application with higher duty cycles a EAPSM material with 30% transmission is preferable.

The semiconductor industry will soon be putting >=1.07NA 193nm immersion lithography systems into production for the 45nm device node and in about three years will be putting >=1.30NA systems into production for the 32nm device node. For these very high NA systems, the maximum angle of light incident on a 4X reticle will reach ~16 degrees and ~20 degrees for the 45nm and 32nm nodes respectively. These angles can no longer be accurately approximated by an assumption of normal incidence. The optical diffraction and thin film effects of high incident angles on the wafer and on the photomask have been studied by many different authors. Extensive previous work has also investigated the impact of high angles upon hard (e.g., F-doped silica) thick (>700μm) pellicles for 157nm lithography, e.g.,. However, the interaction of these high incident angles with traditional thin (< 1μm) organic pellicles has not been widely discussed in the literature. In this paper we analyze the impact of traditional thin organic pellicles in the imaging plane for hyper-NA immersion lithography at the 45nm and 32nm nodes. The use of existing pellicles with hyper-NA imaging is shown to have a definite negative impact upon lithographic CD control and optical proximity correction (OPC) model accuracy. This is due to the traditional method of setting organic pellicle thickness to optimize normally incident light transmission intensity. Due to thin film interference effects with hyper-NA angles, this traditional pellicle optimization method will induce a loss of high spatial frequency (i.e., high transmitted angle) intensity which is similar in negative impact to a strong lens apodization effect. Therefore, using simulation we investigate different pellicle manufacturing options (e.g., multi-layer pellicle films) and OPC modeling options to reduce the high spatial frequency loss and its impact.

Towards hyper-NA lithography, the mask blank and mask topography have the opportunity to be optimized for imaging performance. At the resolution limit of hyper-NA imaging, depth of focus and MEEF become critical for conventional mask stacks. Although conventional binary masks (BIM) are the simplest and the most cost-effective to manufacture, other mask types can provide better imaging performance. This study explores the feasibility and imaging performance of an embedded binary mask (EBM). The EBM emphasizes the simple binary manufacturing process with the application of an additional transparent layer. Two types of EBM's, topographic and planar, were evaluated. The mask diffraction properties are studied by both measurements using an ellipsometer (Woollam VUV-VASE) and simulations using Solid-E 3.2.0.2 (Sigma-C). In this first phase, the imaging performance is assessed by rigorous simulations for three different illumination conditions (cross-quad, quasar and annular). By comparing metrics such as contrast, NILS, MEEF, and process windows, simulations determined that an optimized topographic EBM has a better overall through-pitch imaging performance than a conventional binary mask. This preliminary investigation suggests that an embedded binary mask may be considered as an RET option for hyper-NA imaging improvement.

Scatterometers are widely used for line/space or 2D structure measurements in both wafer and mask industries. This technology is now gaining more acceptance and is being applied 3D structures such as contacts and pads. Contact CDs and trench depth in photomasks are critical monitoring parameters in mask industry and are discussed here. We are reporting contact CDs and profile results measured from targets from Binary, PSM, and Crless plates. The strategies of model creation such as using simple trapezoid versus more advanced shapes affect how well SWA and footings can be measured and reported from these structures. We are reporting CD and profile information obtained with Scatterometer, and then comparing CD SEM, AFM, and cross section SEM. Multiple different modeling configurations were used with different levels of complexity, and we report on optimum modeling strategy to obtain profile information from 3D structures. The relationship between the modeling strategy versus cross correlation between different parameters is discussed. CD linearity, uniformity, and other correlation parameters to the reference CD SEM tool are reported. Target CDs ranged from 60nm up to 600nm. CD uniformity reported from Scatterometry is 20~30% less than that from CD SEMs. This CD uniformity improvement is due to the fact that scatterometer beam samples dozens to hundreds of samples and 'averages' profile parameters, thus eliminating local effect such as line edge roughness. Contact depth are also measured and compared to AFM, in which the bias between the two tools are usually around 3nm or less. In terms of smallest target CD measurable, in this paper we report routine measurement of small contacts with middle CD down to 65nm (bottom CD close to 50nm) with both RP and SE mode. Application of scatterometry method to mask contacts and pads leads to accurate and fast measurement of 3D profiles, and opens up possibility of in-line monitoring of profile information due to the higher runrate compared to traditional metrology tools.

Critical dimension (CD) metrology is an important process step within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately tolerances of device electrical performance drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process and photomask quality. At the 65nm node the ITRS roadmap calls for sub-3nm photomask CD uniformity to support a sub-3nm wafer level CD uniformity. Meeting these targets has proven to be a challenge. What can be inferred from these specifications is that photomask level CD performance is the direct contributor to wafer level CD performance. With respect to phase shift masks, criteria such as phase and transmission control are also tightened with each technology node. A comprehensive study is presented supporting the use of photomask aerial image emulation CD metrology to predict wafer level Across Chip Linewidth Variation (ACLV). Using the aerial image can provide more accurate wafer level prediction because it inherently includes all contributors to image formation such as the physical CD, phase, transmission, sidewall angle, and other material properties. Aerial images from different photomask types were captured to provide across chip CD values. Aerial image measurements were completed using an AIMS^TMfab193i with its through-pellicle data acquisition capability including the Global CDU Map^TM software option for AIMS^TM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CD data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using aerial image CD metrology.

Design Based Metrology (DBM) requires an integrated process from design to metrology, and the very first and key step of this integration is to translate design CD lists to metrology measurement recipes. Design CD lists can come from different sources, such as design rule check, OPC validation, or yield analysis. These design CD lists can not be directly used to create metrology tool recipes, since tool recipe makers usually require specific information of each CD site, or a measurement matrix. The manual process to identify measurement matrix for each design CD site can be very difficult, especially when the list is in hundreds or more. This paper will address this issue and propose a method to automate Design CD Identification (DCDI), using a new CD Pattern Vector (CDPV) library.

The production process of photo-masks for memory devices is highly demanding since homogeneity of mask parameters plays a pivotal role for the overall mask quality. Spatially homogeneous mask designs - which are dominant on memory devices - should in the best case be transferred into a mask exhibiting the same homogeneous behavior. This means that CD deviations from the mean should ideally bear no systematic signature but at most some random noise. However, many steps in the mask production process can introduce spatial correlations so that CD deviations are not only stochastically distributed over the mask but exhibit a pronounced signature. Thus, the determination and quantification of these deviations is crucial for a) assessing the mask quality and b) driving process improvements to remove CD signatures. The most common data analysis method for separating signatures from noise is to average over a number of samples. Unfortunately, due to the nature of mask manufacturing often there is only one sample available. In this paper we propose the technique of Thin Plate Spline Smoothing for the determination and quantification of the CD signature of a given single mask. This analysis is complemented by two statistical tests which assess the fit quality by analyzing the residual for normality and correlations.

The models based on pixelized representation of the photomask have been employed by several authors in order to provide the systematic framework for design of photomask patterns resulting in images with desired optimal properties. One possibility to directly implement such pixel-based optimal mask patterns arises in Optical Maskless Lithography (OML). In one implementation of OML, spatial light modulators (SLMs) are used instead of the photomask. Each SLM may have millions of pixels that can individually change their optical properties utilizing one or the other physical modulation principle (e.g. pistoning micro-mirror pixels or tilting micro-mirror pixels). One important question, applicable to both SLMs used in OML and pixelized photomasks, is: how well is a particular pixel modulation principle suited to obtain the optimal image? We discuss the ways to answer this question, derived from the new methodology of OML rasterization algorithms. The illustrating examples are presented for traditional photomasks (AttPSM) and the SLMs with pistoning micro-mirror pixels. Based on this analysis, we present new examples demonstrating the concept and advantages of "truly maskless" optical maskless lithography.

High resolution mask inspection in advanced wafer fabs is a necessity. Initial and progressive mask defect problem still remains an industry wide mask reliability issue. Defect incidences and its criticality vary significantly among the type of masks, technology node and layer, fab environment and mask usage. A usage and layer based qualification strategy for masks in production need to be adopted in wafer fabs. With the help of a high-resolution direct reticle inspection, early detection of critical and also non-critical defects at high capture rates is possible. A high-resolution inspection that is capable of providing necessary sensitivity to critical emerging defects (near edge) is very important in advanced nodes. At the same time, a way to disposition (make a go / no-go decision) on these defective masks is also very important. As the impact of these defects will depend on not only their size, but also on their transmission and MEEF, various defect types and characteristics have to be considered. In this technical report the adoption of such a high-resolution mask inspection system in wafer fab production is presented and discussed. Data on this work will include inspection results from advanced masks, layer and product based inspection pixel assignment, defect disposition and overall wafer fab strategies in day-to-day production towards mask inspection.

Pushing the limits of optical lithography by immersion technology requires ever smaller feature sizes on the reticle. At the same time the k1-factor will be shifted close to the theoretical limit, e.g. the OPC structures on the reticle become very aggressive. For the mask shop it is essential to manufacture defect free masks. The minimum defect size, which needs to be found reliably, becomes smaller with decreasing feature sizes. Consequently optical inspection of masks for the 45nm node and below will be challenging. In this paper the limits of existing KLA inspection tools were investigated by systematic inspection of different structures without and with programmed defects. A test mask with isolated and dense lines/space patterns including programmed defects was manufactured, completely characterized by CD-SEM and inspected with state-of-the-art inspection system. AIMS^TM measurements were used to evaluate the defect printing behavior. The analysis of the measurement data gives an input for requirements of reticle inspection of upcoming 45nm node and beyond.

Mask inspection and qualification is a must for wafer fabs to ensure and guarantee high and stable yields. Single defect events can easily cause a million dollar loss through a defect duplicating onto the wafer. Several techniques and methods for mask qualification within a wafer fab are known but not all of them are neither used nor understood regarding their limitations. Increasing effort on existing tool platforms is necessary to detect the defects of interest which are at the limit of the tools specification - On the other hand next generation tools are very sensitive and therefore consume only a negligible amount of time for recipe optimization. Knowing the limits of each inspection tool helps to balance between effort and benefit. Masks with programmed defects of 90nm and 65nm design rule were used in order to compare the different available inspection techniques. During the course of this technical work, the authors concentrate mainly on two inspection techniques. The first one inspects the reticle itself using KLA-Tencor's SLF27 (TeraStar) and SL536 (TeraScan) tools. As the reticle gets inspected itself this is the so called "direct" mask defect inspection. The second inspection technique discussed is the "indirect" mask defect inspection which consists of printing the pattern on a blank wafer and use KLA-Tencor's bright-field wafer inspection tool (2xxx series) to inspect the wafer. Data of this work will include description of the techniques, inspection results, defect maps, sensitivity analysis, effort estimation as well as limitations for both techniques for the used design rule.

Aggressive 193nm optical lithography solutions have in turn led to increasingly complex model-based OPC methodologies. This complexity married with the inevitable march of Moore's Law has produced a figure count explosion at the mask writer level. Variable shaped beam equipment manufacturers have tried to mollify the impact of this figure count explosion on the write time by the introduction of new technologies such as increased beam current density, faster DAC amplifiers and more efficient stage algorithms. Despite these efforts, mask manufacturers continue to explore ways of increasing writer throughput and available capacity. This study models the impact of further improvements in beam current density and settling times. Furthermore, this model will be used to prescribe the necessary improvement rates needed to keep pace with the shot count trends extending beyond the 45nm node.

For the half pitch below 45nm, the required sub-resolution feature size is about to be 60nm, and the uniformity of dense lines to be below 3.4nm for the mask fabrication. To achieve this requirement, the reduction of beam blur is necessary. On the mask patterning using 50keV electron beam, the beam blurring due to coulomb interaction and resist characteristics is the main effect of the pattern image degradation and the limit of CD uniformity. In this report, we present the effect of the beam blur induced by coulomb interaction and resist. And we report the recent simulated and experimental results on the resolution change depending on bream blur and design node. Finally, we conclude that the reduction of beam blur can improve the mask quality and there is a compatible condition between the beam blur and the mask fabrication.

A strategy for sub-100 nm technology nodes is to maximize the use of high-speed deep-UV laser pattern generators, reserving e-beam tools for the most critical photomask layers. With a 248 nm excimer laser and 0.82 NA projection optics, the Sigma7500 increases the application space of laser pattern generators. A programmable spatial light modulator (SLM) is imaged with partially coherent optics to compose the photomask pattern. Image profiles are enhanced with phase shifting in the pattern generator, and features below 200 nm are reliably printed. The Sigma7500 extends the SLM-based architecture with improvements to CD uniformity and placement accuracy, resulting from an error budget-based methodology. Among these improvements is a stiffer focus stage design with digital servos, resulting in improved focus stability. Tighter climate controls and improved dose control reduce drift during mask patterning. As a result, global composite CD uniformity below 5 nm (3σ) has been demonstrated, with placement accuracy below 10 nm (3σ) across the mask. Self-calibration methods are used to optimize and monitor system performance, reducing the need to print test plates. The SLM calibration camera views programmed test patterns, making it possible to evaluate image metrics such as CD uniformity and line edge roughness. The camera is also used to characterize image placement over the optical field. A feature called ProcessEqualizer^TM has been developed to correct long-range CD errors arising from process effects on production photomasks. Mask data is sized in real time to compensate for pattern-dependent errors related to local pattern density, as well as for systematic pattern-independent errors such as radial CD signatures. Corrections are made in the pixel domain in the advanced adjustments processor, which also performs global biasing, stamp distortion compensation, and corner enhancement. In the Sigma7500, the mask pattern is imaged with full edge addressability in each writing pass, providing the means of additionally improving write time by reducing the number of exposure passes. Photomask write time is generally under two hours in the 2-pass mode, compared to three hours with 4-pass writing. With a through-the-lens alignment system and both grid matching and pattern matching capabilities, the tool is also suitable for 2^nd layer patterning in advanced PSM applications. Improvements in alignment algorithms and writing accuracy have resulted in first-to-second level overlay below 15 nm (mean+3σ).

CD control requirements for advanced node masks are in the low single digit nanometer range. CD control for Variable Shaped Beam (VSB) lithography that is used to manufacture these masks is dependent on the post-fracture figure layout. Shot linearity, shot size repeatability, and shot placement repeatability can affect CD control differently based on the figure layout. The potential CD error contribution from poorly optimized fracture strategies thus can be a significant contributor to the total CD error. In this paper we present a set of fracture quality metrics based on the impact on mask CD control and methods using EDA software to grade fracture strategies based on these fracture quality metrics. We also discuss applications of this metric for fracture tool design and the implementation of different fracture strategies into mask manufacturing including examinations of the predictability of fracturing results. Finally, we will discuss the usage of existing information about the design (such as design intent) in conjunction with the proposed quality metrics to judge different fracture strategies.

In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the pitch of the processing system. Double patterning technology is a key enabler of printing mask features on wafers as a hybrid extension to optical approaches with new litho-aware design methods and tools, optical equipment, and process flows. The approach does not require restrictions on the design of the chip. This paper will discuss the method and full-chip decomposition tool used to determine locations to split the layout. It will demonstrate examples of over-constrained layouts and how these configurations are mitigated. It will also show the reticle enhancement techniques used to process the split layouts and the Lithographic Checking. A new type of "hotspot" is identified through simulation and tools to identify, repair and verify are shown. Lithography results are shown with effective k₁<0.2 for logic and flash memory patterns.

A series of chromeless multiple-phase shift lithographic test monitors have been previously introduced. This paper investigates various effects that impact the performance of these monitors, focusing primarily on PSM Polarimetry, a technique to monitor illumination polarization. The measurement sensitivities from a variety of scalar and rigorous electromagnetic simulations are compared to experimental results from three industrial quality multi-phase test reticles. This analysis enables the relative importance of the various effects to be identified and offers the industry unique insight into various issues associated with the photomask. First, the unavoidable electromagnetic interaction as light propagates through the multiple phase steps of the mask topography appears to account for about 10 to 20% of the lost sensitivity, when experimental results are compared to an ideal simulated case. The polarization dependence of this effect is analyzed, concluding that the 4-phase topography is more effective at manipulating TM polarization. Second, various difficulties in the fabrication of these complicated mask patterns are described and likely account for an additional 60-80% loss in sensitivity. Smaller effects are also described, associated with the photoresist, mask design and subtle differences in the proximity effect of TE and TM polarization of off-axis light at high numerical aperture. Finally, the question: "How practical is PSM polarimetry?" is considered. It is concluded that, despite many severe limiting factors, an accurately calibrated test reticle promises to monitor polarization in state-of-the-art lithography scanners to within about 2%.

Chromeless Phase Lithography (CPL) is discussed as interesting option for the 65nm node and beyond offering high resolution and small Mask Error Enhancement Factor. However, it was shown recently that at high NA CPL masks can exhibit large polarization and also phase effects. A well known phase effect occurring for CPL semi dense lines are through focus Bossung tilts. However, another manifestation of phase effects for dense lines and spaces is a reduced contrast for a symmetrical off-axis illumination due to phase errors between 0^th and 1^st diffraction order. In this paper it is shown that these phase effects can lead to a significant contrast loss for dense features smaller than 60nm half pitch. While also present for trench structures, the contrast reduction is more pronounced for mesa style structures. It is shown that for mesa structures an adjustment of etch depth can not recover an effective pi-phase shift. Furthermore, significant polarization effects are observed. As an example, the optimum mesa structure for TE polarization is shifted to small lines. For an experimental validation, a CPL mask containing dense lines and spaces was fabricated. Their imaging performance was characterized with an AIMS 45i offering NA's greater than 1 and linearly polarized illumination as well as by wafer printing. Gratings with pitches down to 100 nm with varying duty cycles were measured with TE, TM and unpolarized dipole illumination. Very good agreement between measurement and simulation results confirmed the validity of theoretical predictions.

New advanced mask rule checking (MRC) solutions are required to ensure cost effective, high yield photomask manufacturing processes at 65nm and below and are needed to provide new verification capabilities for mask makers and data prep engineers alike. Traditional MRC, which implements fundamental geometric data checks on limited data formats, is not sufficient for advanced photomask manufacturing. Like recent advances in design rule checking (DRC) software, which includes extensive "manufacturing-aware" rules (or DFM rules), MRC solutions must evolve to include a more comprehensive and intelligent rule checks for the mask manufacturing process. This paper describes the development and testing of an advanced MRC software solution developed within the CATS^TM mask data preparation (MDP) solution from Synopsys Inc. The new MRC solution enables the inspection and analysis of mask layout patterns for simple and advanced data verification checks. Proposed applications for mask data prep applications are discussed and include incoming design verification, fracture data correction, inspection tool data tags, mask manufacturing tool or inspection tool selection, and job deck verification.

"Sub-resolution assist features" (SRAFs) are a standard "resolution enhancement technique" (RET) to ensure the lithography process window of narrow lines for critical mask levels. Since placement rules for SRAFs commonly demand a fixed, constant separation from the edges of the main features to be assisted, small jogs and notches in the layout of the main features force an SRAF interruption. As a consequence, locally the process window is reduced. In addition, jogs and notches increase the data amount and may cause an increase of run time of "design rule check" (DRC), "optical proximity correction" (OPC), and "mask data preparation" (MDP). In most cases, these jogs and notches are completely unnecessary for the electrical functionality of the circuit and the design rule compliance of the layout. In order to detect such superfluous layout features and give the physical designer the opportunity to remove them, a new approach to design rule checking was developed. This approach is based on the decomposition of the layout of one mask level into its basic geometrical features (e.g., corners, line ends, junctions) and a subsequent classification of these features according to their topology under consideration of electrically related other mask levels (e.g., metal + via = contact pad). We describe the implementation of a generic DRC for the detection of jogs and notches using this approach and highlight the stability and ease of maintenance of this method.

Mask specification has been playing ever-increasing role for wafer process optimization with tightening design rule. It is very critical to optimize specifications and sampling sizes to ensure quality as well as minimize cost and TPT for high volume manufacturing. In this paper, key parameters for mask specification affecting wafer litho process window will be discussed. Examples of how to derive key mask specification based on the litho process margin will be examined. The mask CD targeting control and plate to plate CD variation reduction strategy will be discussed.

After model-based OPC and layer generation, the size of mask data is increasing beyond the limit that current software and hardware can handle. The file size of one of 512M DRAM mask data was 29 GB in GDSII and it could be reduced to 1.7 GB by transforming into OASIS. Compared to GDSII, OASIS included many effective features that could reduce the file size incredibly. In this paper, we adopted the repetitions in OASIS and used the concept to reduce the memory usage of mask data preparation software. We built a new data structure, called shape array that utilizes the repetition of mask data. Mask data is saved in OASIS and its repetition information is loaded onto memory. The data structure can be the basis for the mask data preparation operations such as region query, AND, XOR and so on. We implemented the region query in this paper. The region query is a major operation that a layout viewer uses. The mask data comparison operation, which is used to check the integrity of the mask data, is implemented with the shape array as well. The shape array method has used the memory of between 2 and 22 times less than the method that keeps the coordinate and attributes of each shape individually. The file loading time and the file writing time have improved 4~73 times and 1.5~14 times, respectively.

The quality of model-based OPC correction depends strongly on how the model is calibrated in order to generate a resist image as close to the desired shapes as possible. As the k1 process factor decreases and design complexity increases, the correction accuracy and the model stability become more important. It is also assumed that the stability of one model can be tested when its response to a small variation in one or several parameters is small. In order to quantify this, the small-variation method has been tested on a variable threshold based model initially optimized for the 65nm node using measurements done with a test pattern mask. This method consists of introducing small variations to one input model parameter and analyzing the induced effects on the simulated edge placement error (EPE). In this paper, we study the impact of small changes in the optical and resist parameters (focus settings, inner and outer partial coherent factors, NA, resist thickness) on the model stability. And then, we quantify the sensitivity of the model towards each parameter shift. We also study the effects of modeling parameters (kernel count, model fitness, optical diameter) on the resulting simulated EPE. This kind of study allows us to detect coverage or process window problems. The process and modeling parameters have been modified one by one. The ranges of variations correspond to those observed during a typical experiment. Then the difference in simulated EPE between the reference model and the modified one has been calculated. Simulations show that the loss in model accuracy is essentially caused by changes in focus, outer sigma and NA and lower values of optical diameter and kernel count. Model results agree well with a production layout.

The properties of phase shifting attenuator films are quantified in a variety of ways. Transverse dimensions are measured by optical microscopes or scanning electron microscopes. Vertical dimension and profiles are measured by atomic force microscopes or indirectly by optical scatterometry. The complex refractive index of an attenuator film can be characterized by ellipsometry or by spectroscopic analysis of reflected and transmitted light. Transmission and phase measurements can be made with optical interferometric techniques. Data acquired in these ways can be used as inputs to simulation programs to model the image forming characteristics of the films. For simplicity and speed of calculation, the simulation programs typically use a thin-mask approximation, in which the vertical absorber geometry is ignored and the phase shifting attenuator regions are characterized only by their transmission, phase shift, and two-dimensional geometric shapes. Inclusion of the full three-dimensional profile and complex refractive index of the absorber can be done, but at the cost of greatly increased calculation time and a loss of the simplicity of understanding afforded by the thin-mask model. For example, the thin-mask model assumes that every geometrical feature etched into a given attenuator film will have the same phase and transmission properties. Comparison of thin-mask modeling results with the full three dimensional model shows that this assumption is not true. The effective dimensional bias, phase, transmission, and defocus are strong functions of the feature size, pitch, and complex refractive index of the film. Three dimensional simulations were run for several commercial and developmental high-transmission phase-shifting attenuator films. The effective phase and dimensional printing bias were calculated as a function of pitch for each film. Surprising differences were found in the results for the various film types.

The 2005 edition of the International Technology Roadmap for Semiconductors specifies that phase errors of alternating phase-shifting masks (APSM) should approach ± 1 degree by 2008. This specification is reasonably motivated by the desire to keep imaging effects of mask errors below those of aberrations of projection optics, but it implies a questionable assumption that the phase of a feature is a well-defined quantity. Variations of both phase and amplitude across apertures are significant. In addition to the variables that we expect mask manufacturers to control, such as trench depth, wall slope, and bottom-surface flatness, phase also depends on polarization, illumination angle, widths of apertures, and proximity of other features. Dependence of phase on variables in addition to trench depth will increase as we shrink to pitches available with immersion lithography, perhaps restricting layouts that can be printed with APSM technology. Mask manufacturers must develop methods to set and measure phase to necessary tolerance.

Cutting edge technology node manufacturers are always researching how to increase yield while still optimally using silicon wafer area, this way these technologies will appeal more to designers. Many problems arise with such requirements, most important is the failure of plain layout geometric checks to capture yield limiting features in designs, if these features are recognized at an early stage of design, it can save a lot of efforts at the fabrication end. A new trend of verification is to couple geometric checks with lithography simulations at the designer space. A lithography process has critical parameters that control the quality of its resulting output. Unfortunately some of these parameters can not be kept constant during the exposure process, and the variability of these parameters should be taken into consideration during the lithography simulations, and the lithography simulations are performed multiple times with these variables set at the different values they can have during the actual process. This significantly affects the runtime for verification. In this paper the authors are presenting a methodology to carefully select only needed values for varying lithography parameters; that would capture the process variations and improve runtime due to reduced simulations. The selected values depend on the desired variation for each parameter considered in the simulations. The method is implemented as a tool for qualification of different design techniques.

This work represents one in a series of ongoing papers demonstrating the potential utility of integrating advanced photolithographic simulation software into a mask repair tool to provide immediate defect or repair printability feedback. The equipment used here is an AFM-technology based nanomachining photomask repair tool where the high-accuracy AFM surface topography data is fed directly into software applying rigorous solutions to Maxwell's equations. The nature of these systems allows for process endpoint printability evaluation, not restricted by the optical limitations of any given apparatus, of any micro to nano-scale region of the mask concurrent with the normal defect repair process. However, known AFM scan artifacts can impact the accuracy and stability of the photolithographic simulation results, especially for mask or pattern types which have not been previously studied by the user. The relevant sources of these artifacts are identified and improvements in the AFM operation are discussed which could minimize them. The quantitative relationships between the various artifact measures and their corresponding effects on various simulation results (including relative transmission and CD) are examined for both AIMS^TM aerial imaging and wafer print. From this examination, error baselines are established and software, as well as model setup, optimizations are proposed.

We have reported the FIB repair system with low acceleration voltage is applicable to 65nm generation photomasks. Repair technology beyond 65nm generation photomasks requires higher edge placement accuracy and more accurate shape. We developed two new functions, "Two Step Process" and "CAD Data Copy". "Two Step Process" consists of primary process and finishing process. The primary process is conventional process, but the finishing process is precise process to control repaired edge position with sub-pixel order. "Two Step Process" achieved edge placement repeatability less than 3nm in 3sigma. At "CAD Data Copy", defects are recognized with comparison between shape captured from a SIM image and that imported from a CAD system. "CAD Data Copy" reproduced nanometer features with nanometer accuracy. Thus the FIB repair system with low acceleration voltage achieves high performance enough to repair photomasks beyond 65nm generation by using "Two Step Process" and "CAD Data Copy".

To overcome several drawbacks of the standard pattern copy procedure used to create the repair shape(s) for a particular defect site, we have developed and implemented a layout based pattern copy method (a.k.a. "database pattern copy"). In general, pattern copy derives the repair structure by comparing a high resolution image of the defective area with the same image of a non-defective area. The repair shape is generated as the difference of these two images, and adjusted for processing purposes. As opposed to the conventional pattern copy method, which derives the reference using information taken from the mask under repair, the new method uses reference information from the original mask design file. As a result, it reduces the CD error of the repair, simplifies the repair process work flow, and greatly reduces the potential of operator error. We present the new method along with experimental results taken from programmed defect repair on our MeRiT MG^TM production tool.

After quartz blanks with various sulfate ion amount on the surfaces were exposed by an ArF laser, growing defects, haze, on the surfaces were consequently counted by an inspection tool. As a result, the number of haze largely depends on the sulfate ion amount, and it is found that no haze is generated when the sulfate ion amount is smaller than a threshold value. A new haze generation model is provided to explain the threshold phenomenon. And then storage impact on increase of the sulfate ion amount was investigated. The sulfate ion amount increases with storage time and airborne SO_x concentration. From the results, the adsorption coefficient of an extended Langmuir equation was calculated, and the adsorption phenomenon was analyzed in detail. Simulation results show that it is recommended, regarding for storage environment, to keep under 0.01 ppbv airborne SO_x concentration in order to prevent haze for one year.

It is important to understand how the outgassed chemicals from pellicle materials are involving in various surface reactions towards haze defect formation on the mask surface during the exposure. In this work, we have analyzed the gaseous environment and the substrate surface under laser exposure in the specially designed quartz tube filled by air, or N2. We observed that various chemicals that consist of the pellicle film are outgassed from the film and then deposited or interact with other chemicals to make haze defects on the substrate surface during laser exposure. This fact can be further applied not only to the study of pellicle outgassing effect on haze defect growth mechanism but also to the development of real-time monitoring tools for the defect growth progress on the mask surface.

Existing cleaning technology using sulfuric acid based chemistry has served the mask industry quite well over the years. However, the existence of residue on mask surfaces is becoming more and more of a problem at the high energy wavelengths used in lithography tool for wafer manufacturing. This is evident by the emergence of sub-pellicle defect growth and backside hazing issues. A large source of residual contamination on the surface of masks is from the mask manufacturing process, particularly the cleaning portion involving sulfuric acid. Cleaning strategies can be developed that eliminate the use of sulfuric acid in the cleaning process for advanced photomasks and alternative processes can be used for cleaning masks at various stages of the manufacturing process. Implementation of these new technologies into manufacturing will be discussed as will the resulting improvements, advantages, and disadvantages over pre-existing mask cleaning processes.

As the on-wafer transistor sizes shrink, and gate nodes reduce below 90 nm, it is becoming very important to precisely measure and control the critical dimension (CD) on the mask. Phase shift technology for masks is essential for decreasing of the feature size, therefore CD and profile metrology on the phase shifting materials becomes critical. Scatterometry provides fast and nondestructive method of profile and CD measurements. In this paper the conditions of determining of profile and CD measurement are analyzed. In the real experiment scattered spectrum from structure with unknown profile is measured. Before experiment the library of spectra is generated. Spectra in the library correspond to structures with various parameters (such us thickness, CD, sidewall angle, etc.). For calculation of this library rigorous coupled-wave analysis (RCWA) was used. This method allows us to get precise solution of Maxwell equations and find directly amplitude of zero diffraction order which is measured in the experiment. To determine the possibility of measurement of sidewall angle various spectra with different sidewall angle value were calculated. Calculated spectrum is changed by adding or deduction of random value. The randomly changed spectrum is compared with spectra in the library in order to find spectrum with best fit. Therefore sidewall angle and CD can be determined. Precision, possibility and maximum allowed error in the spectra measurements is obtained. Moreover, influence of polarization of incident light on precision of extracted results was found.

Photomask inspection requires a combination of high resolution and high throughput. Scanning electron microscopy (SEM) has excellent resolution but at high throughput yields noisy images. Hence we are developing algorithms for extracting pattern information from noisy SEM images. One big challenge in processing SEM images is edge extraction. SEM images have their own characteristics so many existing edge extraction algorithms based on gradient signal analysis do not work well in that they either yield strong signal for non-edge areas or yield weak signal for true edge areas. We describe several new edge extraction algorithms targeting noisy SEM images. The essence of these new algorithms is analyzing the "ridge" signal, i.e., the bright stripes. We first propose edge extraction based on second-order polynomial regression. Based on the observation that the pixel values around edges in SEM images behave approximately as second-order polynomial functions of coordinates, we compute the "ridge" signal using the coefficients of such polynomial functions obtained from regression. This algorithm generally yields very accurate estimation of the edge locations, especially for straight edges. In the approach based on second-order polynomial regression, it is implicitly assumed that the edge is (approximately) straight. We thus propose a further improvement on this algorithm and assume that edge shapes can be well approximated by second-order curves, even at sharp turns. This approximation leads to a fourth-order polynomial regression with better performance around edges with a sharp turn. A third algorithm is based on image segmentation. Image segmentation, which is mostly used in image content analysis, is defined as the partition of a digital image into multiple regions (sets of pixels) so that the objects of interest are separated from the background. In our approach, we adapt image segmentation to edge extraction. In particular, we apply a fast segmentation algorithm to separate the bright area from the dark area, and use the difference of average pixel values as the "ridge" signal. The advantage of this approach is that no assumption on the edge shape is involved and the computational complexity is low. Finally, we propose a hybrid algorithm combining the segmentation approach and the polynomial regression approach, yielding a "segmentation-assisted" algorithm that incorporates the advantages of both approaches. Simulation on a wide range of SEM image types yields quite satisfactory results, even for very noisy images. We will present detailed algorithm flows and demonstrate extraction results from real images.

Following the international technology roadmap for semiconductors the image placement precision for the 65nm technology node has to be 7nm. In order to be measurement capable, the measurement error of a 2D coordinate measurement system has to be close to 2nm. For those products, we are using the latest Vistec registration metrology tool, the LMS IPRO3. In this publication we focus on the tool performance analysis and compare different methodologies. Beside the well-established ones, we are demonstrating the statistical method of the analysis of variance (ANOVA) as a powerful tool to quantify different measurement error contributors. Here we deal with short-term, long-term, orientation-dependent and tool matching errors. For comparison reasons we also present some results based on LMS IPRO2 and LMS IPRO1 measurements. Whereas the short-term repeatability and long-term reproducibility are more or less given by the tool set up and physical facts, the orientation dependant part is a result of a software correction algorithm. We finally analyse that kind of residual tool systematics and test some improvement strategies.

As feature size is shrinking and MEEF (Mask error enhancement factor) is increasing, CD measurement accuracy is more important, and CD SEM is widely used to replace optic tools because of their resolution. But CD-SEM is not representing the effect of Cr profile or transmittance of light which is transferred to wafer. Recently, new OCD (optic CD) tool which use scatterometry (Spectroscopic Ellipsometry) ^*1) is introduced to compensate the demerit of SEM of low through-put and reflected surface information of mask. This scatterometry tool can be used only on periodic pattern like DRAM. And this tool must be calibrated on each pattern type and shape. This calibration is the barrier to use this scatterometry method to mask process where all masks are processed one time. In this work, new optical CD measurement method which use conventional optic microscope of transmitted and reflected light with high resolution lens of DUV on periodic patterns is introduced. To enhance the accuracy of measurement, interpolating method and FFT (Fast Fourier Transform) are used. CD measurement results of linearity by optic CD, SE and CD-SEM were compared on several patterns. And CD variations on full field of image were evaluated on L/S patterns and active layer of DRAM.

The fabrication of a production-worthy phase shift mask requires, among other things, excellent uniformity of critical dimensions (trench width and depth) and optical properties of the phase shift material (MoSi). Traditionally, CD-SEM has been the instrument of choice for the measurement of width; AFP (Atomic Force Profilometer) or conventional profilometer for the measurement of depth; and Interferometer for the measurement of phase shift and transmittance of the phase shift material. We present an innovative optical metrology solution based on broadband reflectometry, covering a wavelength range from 190 to 1000 nm, in one nanometer intervals. The analysis is performed using Forouhi-Bloomer dispersion equations, in conjunctions with Rigorous Coupled Wave Analysis (RCWA). The method provides accurate and repeatable results for critical dimensions, thickness, and optical properties (n and k spectra from 190 - 1000 nm) for all materials present in the structure. In the current study, the method described above was used to examine photomasks at two stages of mask manufacturing process: After Etch Inspection (AEI) and After Strip Inspection (ASI). The results were compared with the measurements taken on the same samples using conventional CD-SEM. Two comparison studies were conducted - global CD uniformity and CD linearity. The CD linearity study demonstrated excellent correlation between the values of grating line width obtained using this new optical reflectometry approach and a CD-SEM for the grating structures of two pitches (760 nm and 1120 nm). The global CD uniformity study revealed that this presented reflectometry method can be used to produce CD uniformity maps which demonstrate excellent correlation with the results obtained using a conventional CD-SEM. The advantages of the optical method are high throughput, non-destructive nature of the measurements and capability to measure a wider variety of structures pertinent to the photomask manufacturing process.

Immersion lithography and multiple exposure techniques are the most promising methods to extend lithography manufacturing to the 45nm node. Although immersion lithography has attracted much attention recently as a promising optical lithography extension, it will not solve all the problems at the 45-nm node. The 'dry' option, (i.e. double exposure/etch) which can be realized with standard processing practice, will extend 193-nm lithography to the end of the current industry roadmap. Double exposure/etch lithography is expensive in terms of cost, throughput time, and overlay registration accuracy. However, it is less challenging compared to other possible alternatives and has the ability to break through the κ₁ barrier (0.25). This process, in combination with attenuated PSM (att-PSM) mask, is a good imaging solution that can reach, and most likely go beyond, the 45-nm node. Mask making requirements in a double exposure scheme will be reduced significantly. This can be appreciated by the fact that the separation of tightly-pitched mask into two less demanding pitch patterns will reduce the stringent specifications for each mask. In this study, modeling of double exposure lithography (DEL) with att-PSM masks to target 45-nm node is described. In addition, mask separation and implementation issues of optical proximity corrections (OPC) to improve process window are studied. To understand the impact of OPC on the process window, Fourier analysis of the masks has been carried out as well.

Sub-resolution Assist Features (SRAFs) are powerful tools to enhance the focus margin of drawn patterns. SRAFs are sized so they do not print on the wafer, but the larger the SRAF, the more effective it becomes at enhancing through-focus stability. The size of an SRAF that will image on a wafer is highly dependent upon neighboring patterns and models of SRAF printability are, at present, unreliable. Conservative SRAF rules have been used to ensure that SRAFs never print on a pattern. More accurate models of SRAF printing should allow SRAF rules to be relaxed, resulting in more effective SRAF placement and broader focus margins. The process models that are used during Optical Proximity Correction have never been able to reliably predict which SRAFs will print on a pattern. This appears to be due to the fact that OPC process models are generally created using data that does not include subresolution patterns. In addition, the definition of a printing SRAF is not clear, as it can range from a photoresist film left on a wafer to a pattern that is transferred to the substrate during the etch process. This paper will demonstrate a model that identifies SRAFs which appear in photoresist and those which survive the etch step.

With moving from one process node to another, process effect corrections are becoming a very challenging task. High quality models, long run times and extensively large computer resources are needed to perform a typical modern process effect correction procedure. Since the patterns that form IC layouts are highly repetitive, all the modern process correction algorithms try to take advantage of this fact to decrease processing time and computer resources requirements. However, currently used high accuracy process effect correction algorithms are becoming less and less advantageous because of the increasing relative non-locality of the process effects. In this paper, we investigate the feasibility of a simpler approach called "cell-wise corrections". We propose a recipe for the cell-wise process effect correction and analyze its accuracy using a 65 nm test layout. The recipe is fully automated and implemented using a commercially available OPC tool. The analysis reveals good accuracy and feasibility of our approach.

Across-chip and across-wafer patterned linewidth variation (ACLV and AWLV respectively) as well as linewidth roughness (LWR) are key contributors to device performance variation. For polysilicon gate patterning, the linewidth control enabled by various phase-shift mask (PSM) design approaches is one of the key metrics in selecting the most manufacturable process. Embedded attenuated PSM (6% EAPSM), chromeless PSM (CPL) and alternating aperture PSM (AAPSM) designs were selected for comparison. Polysilicon wafers were exposed with 193nm lithography using these reticles, and then ACLV, AWLV and LWR were measured for each PSM process. The results are discussed and compared with other reticle design factors important for effective 65nm node patterning in production.

The fast pattern shrinkage of DRAM has driven the lithography technology into the low k1 regime for sub-60 nm technology node. There are a lot of resolution enhancement techniques (RETs) e.g. OPC (Optical Proximity Correction), SB (Scattering Bar), SRAF (Sub-Resolution Assist Features) and DDL (Double Dipole Lithography) and Alternating PSM to enable the low k1 lithography [4]. However, among the RETs, the alternating PSM technique is a high cost solution because double exposure is needed to avoid phase conflict error. Therefore, the implementation of alternating PSM with single exposure for gate conductor layer is the main purpose of this study. Many kinds of pattern and phase designs in the main cell and periphery were investigated.

With decreasing the design node, there are some candidates for the optical lithography technology. Double Exposure Technology (DET) is the one of the solution to extend the resolution limit down to k1 less than 0.25 for the next generation devices. To accomplish DET, photomask MTT, CD uniformity, and the overlay between the layers for the dual exposure are important as the photomask process aspect. MTT and CD uniformity have been frequently discussed for Single Exposure Technology (SET), but the overlay and the registration have not been discussed yet with the view of DET. In this work, the feasibility of mask fabrication, especially the overlay and the registration for DET are analyzed. The current mask limit of DET is discussed considering MTT, uniformity, and overlay.

The attenuated phase-shift mask (att. PSM) is one of resolution enhancement technologies (RET) and has been widely adopted for several device layers. And the high-transmission att. PSM, which has various structures and transmittances, can be expected to have the advantages in process window. In this paper, the lithographic performances (Contrast, MEEF and DOF) of high-T att. PSM were evaluated by using the 3D electro-magnetic field simulator. The results showed that high-T att. PSM has better MEEF and partially better DOF than those of 6%-transmission MoSi type. As the transmittance is getting higher, the smaller line CD is needed for OPC adjustment especially at narrow pitch. In respect of film structure, it is found that there is no large difference among three high-T att. PSMs except for MEEF at specific pitch. Remaining chrome on the high-T films causes the trade-off between contrast and MEEF. The simulation results are compared with AIMS results measured by AIMS^TM 45-193i of Carl Zeiss. The AIMS results of actual masks agree with no-Hopkins mode simulation very well, while they do not agree with Hopkins mode simulation especially at narrow pitch. Because the azimuthal polarization does not cause contrast loss, the differences between AIMS mode (conventional) and Scanner mode (vector effect emulation) are small.

This paper addresses a challenge to the concept of process window OPC (PWOPC) by investigating the dimensional control of effectively non-printing features to improve the process window (PW) of the primary layout. It is shown based on a double exposure (DE) alternating phase-shift mask (altPSM) process that neglecting the impact of final mask dimensions forming intermediate images in resist (which are subsequently removed with a second exposure) potentially leads to a significant variation in the available focus budget of neighboring linewidth-critical feature dimensions. Various rules-based and model-based options of introducing virtual OPC targets into the OPC flow are discussed as an efficient mean to allow the OPC to take process window considerations into account. The paper focuses especially on the mechanics of how in detail those virtual targets support the beneficial OPC convergence of affected edges. Finally, experimental proof is shown that introducing non-printing, virtual targets being considered as actual targets during OPC ensures enhanced through focus line width stability and hence making the OPC solution well aware of process window aspects.

It is widely understood that the IC Industry's adherence to Moore's Law is widening the gap between the wavelength of light used in semiconductor manufacturing and the features that they define. Increasingly, the patterning community has turned to higher complexity imaging solutions to fill the gap. This steadily increasing complexity is placing a new burden on lithographers and resolution enhancement technology engineers to guarantee that the highly complex patterning strategies will work for all patterns. Traditionally, lithography strategies have been characterized using relatively simple one-dimensional "litho test patterns." Real circuits are highly randomized however, and complex two-dimensional interactions are the rule rather than the exception. This paper extends the paradigm for use of newly available post-OPC verification (POV) technology to the realm of RET development. We offer a case study where two competing 65-nm logic node sub-resolution assist feature (SRAF) strategies for poly layer patterning are evaluated on a full chip using commercially available post-OPC verification technology. We are able to evaluate differences in CD control process window, SRAF printability (illustrated in Figure 1), MEEF sensitivity, and catastrophic defect propensity. In several critical cases, we show silicon confirmation of the simulated results. This methodology allows leveraging of existing full-chip POV technology to enable the selection of the best SRAF strategy with minimal use of costly split lot silicon.

Conventional OPC, also known as site-based OPC, has relied on rules-based fragmentation and site placement since its inception. The issues that arose in earlier generations around imprecise site and fragmentation placement, relative to the exact location of proximity effects, has been illustrated in earlier works [1] but generally did not produce catastrophic results. However, when coupled with the large process biases, strong RET, and accuracy requirements for 45 nm and future nodes, this imprecision can produce catastrophic results. This work will report on efforts to use model-directed site and fragmentation placement, as well as inclusion of process window knowledge into the site-based OPC flow to address varied sources of errors and relative results with different approaches. In addition to the conventional site-based OPC, a new breed of tool that avoids sites in favor of fully gridded, or dense, simulation is rapidly maturing. The new approach allows more intelligence to be built into the OPC engine such that fragmentation and error sampling are more automated and thus less error prone. Using the same layout data, we will also present a snapshot of the new tool's results.

We present a methodology for building through-process, physics-based litho and etch models which result in accurate and predictive models. The litho model parameters are inverted using resist SEM data collected on a set of test-structures for a set of exposure dose and defocus conditions. The litho model includes effects such as resist diffusion, chromatic aberration, defocus bias, lens aberrations, and flare. The etch model, which includes pattern density and particle collision effects, is calibrated independently of the litho model, using DI and FI SEM measurements. Before being used for mask optimization, the litho and etch models are signed-off using a set of verification structures. These verification structures, having highly two-dimensional geometries, are placed on the test-reticle in close vicinity to the calibration test-structures. Using through-process DI and FI measurement and images from verification structures, model prediction is compared to wafer results, and model performance both in terms of accuracy and predictability is thus evaluated.

As the technology node shrinks, printed-wafer shapes show progressively less similarity to the design-layout shapes, even with optical proximity correction (OPC). Design tools have a restricted ability to address this shape infidelity. Their understanding of lithography effects is limited, taking the form of design rules that try to prevent "Hot Spots" - locations that demonstrate wafer-printing problems. These design rules are becoming increasingly complex and therefore less useful in addressing the lithography challenges. Therefore, design tools that have a better understanding of lithography are becoming a necessity for technology nodes of 65 nm and below. The general goal of this work is to correct lithography Hot Spots during physical-design implementation. The specific goal is to automatically fix a majority of the Hot Spots in the Metal 2 layers and above, with a run time on the order of a few hours per layer. Three steps were taken to achieve this goal. First, Hot Spot detection was made faster by using rule-based detection. Second, Hot Spot correction was automated by using rule-based correction. Third, convergence of corrections was avoided by performing correction locally, which means that correcting one Hot Spot was very unlikely to create new Hot Spots.

Emerging resist and etch process technologies for the 45 nm node exhibit new types of non-optical proximity errors, thus placing new demands on OPC modeling tools. In a previous paper (SPIE Vol. 6283-75) we had experimentally demonstrated a full resist and etch model calibration and verified the stability of the model using 45nm node standard logic cells. The etch model used a novel non-linear etch modeling object in combination with conventional convolution Kernels. Building upon those results, this paper focuses on the correction of patterns. We demonstrate a two-stage optical/resist and etch correction using calibrated models, including the use of non-linear etch modeling objects. Optical/resist and etch models are built separately and used sequentially to correct a 45nm logic pattern. Critical areas of the pattern affected by etch are analyzed and used to verify the correction. Verification of the correction is obtained through comparison between the simulated contours with the design intent.

Double patterning technology (DPT) is a promising technique that bridges the anticipated technology gap from the use of 193nm immersion to EUV for the half-pitch device node beyond 45nm. The intended mask pattern is formed by two independent patterning steps. Using DPT, there is no optical imaging correlation between the two separate patterning steps except for the impact from mask overlay. In each of the single exposure step, we can relax the dense design pattern pitches by decomposing them into two half-dense ones. This allows a higher k₁ imaging factor for each patterning step. With combined patterns, we can achieve overall k₁ factor that exceeds the conventional Rayleigh resolution limit. This paper addresses DPT application challenges with respect to both mask error factor (MEF) and 2D patterning. In our simulations using DPT with relaxed feature pitch for each exposure step, the MEF for the line/space is fairly manageable for 32nm half-pitch and below. The real challenge for the 32nm half-pitch and below with DPT is how to deal with the printing of small 2D features resulting from the many cutting sites due to feature decomposition. Each split of a dense pattern generates two difficult-to-print line-end type features with dimension less than one-fifth or one-sixth of ArF wavelength. Worse, the proximity environment of the 2D cut features can then become quite complex. How to stitch them correctly back to the original target requires careful attention. Applying target bias can improve the printing performance in general. But using a model-based stitching error correction method seems to be a preferred solution.

Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits manufactured with optical lithography technology. The accuracy of these models highly depends on the experimental data used in the model development and on the appropriate selection of the model parameters. The optical and resist model parameters selected during model build have a significant impact on the OPC model accuracy, run time, and stability. In order to avoid excessively high run times as well as ensure acceptable results, a compromise must be made between OPC run time and model accuracy. The modeling engineer has to optimize the necessary model parameters in order to find a good trade-off that achieves acceptable accuracy with reasonable run time. In this paper, we investigate the effect of some selected optical and resist model parameters on the OPC model accuracy, run time, and stability.

The transition to the 65nm technology node requires improved methodologies for model based optical proximity correction. The approaches used for previous generations might not be able to deliver the high accuracy which is necessary for gate patterning on high performance or low leakage circuits. A new categorization scheme for OPC fragments will be introduced, which then allows independent optimization for various OPC tool parameters. The feasibility of this technique will be demonstrated by quantifying the OPC convergence through iterations, which emphasizes the performance gain in OPC accuracy and runtime.

As geometries shrink faster than the actual wavelength used for exposure, the Proximity influence distance, or PID of nearest neighbor features starts to impact not only the overall RET of unit cells in the design library but also the flattening of the hierarchy of the electronic design increasing the overall database size, computational times and respective memory requirements per computational node. In this paper we explore the impact of different PID values in relation to the overall flattening of hierarchy, time to market and the impact on RET complexity as dimensions are shrunk in overall design.

A given technological node (45 nm, 65 nm) can be expected to process thousands of individual designs. Iterative methods applied at the node consume valuable days in determining proper placement of OPC features, and manufacturing and testing mask correspondence to wafer patterns in a trial-and-error fashion for each design. Repeating this fabrication process for each individual design is a time-consuming and expensive process. We present a novel technique which sidesteps the requirement to iterate through the model-based OPC analysis and pattern verification cycle on subsequent designs at the same node. Our approach relies on the inference of rules from a correct pattern at the wafer surface it relates to the OPC and pre-OPC pattern layout files. We begin with an offline phase where we obtain a "gold standard" design file that has been fab-tested at the node with a prepared, post-OPC layout file that corresponds to the intended on-wafer pattern. We then run an offline analysis to infer rules to be used in this method. During the analysis, our method implicitly identifies contextual OPC strategies for optimal placement of RET features on any design at that node. Using these strategies, we can apply OPC to subsequent designs at the same node with accuracy comparable to the original design file but significantly smaller expected runtimes. The technique promises to offer a rapid and accurate complement to existing RET application strategies.

A survey-based, empirical study that benchmarks the productivity of photomask manufacturers has led to some significant conclusions. Firstly, the wide variation in the productivity indicators from company to company suggests that all participants may have significant cost-reduction opportunities within their operations. Secondly, the high downtime of pattern generation tools is limiting productivity. Thirdly, producing smaller feature sizes is correlated to an investment in engineering and experimentation capacity. It could not be confirmed that photomask manufacturers are successfully taking advantage of economies of scale.

In the photo-lithography process, a mask is one of the most important items because CD error from its imperfection is transferred to the CD error on the wafer. And the CD error amplification from the mask CD to the wafer CD is denoted by Mask Error Enhancement Factor (MEEF). As the device shrinks so fast, MEEF increases conspicuously and massive OPC is necessary to secure the target pattern CD and the proper process margin on the wafer. Therefore the mask CD uniformity and the just mean-to-target (MTT) are very important to minimize the CD variation on the wafer level. In most cases, MTT and CD uniformity for a certain device are not defined exactly. What we know is that the smaller, the better. Because just small value of MTT and CD uniformity is not the reasonable guideline for the mask fabrication and inducing high mask cost, defining the logical MTT and CD uniformity prospect for a certain device or layer is very important. As the necessity of the low k₁ process increases, MTT and CD uniformity specifications become tighter and tighter. However the proper mask specification for sub-65nm real device has not been defined yet and not been studied considering the mask fabrication and MEEF. In this study, MTT and CD uniformity specification of the sub-65nm real device patterns are discussed with respect to the mask pattern linearity and MEEFs. Mask linearity is one of the typical items for the mask fabrication and strongly related to MTT and CD uniformity. MTT and CD uniformity tolerance also follows OPC tolerance, and OPC tolerance is directly related to the pattern layouts and MEEF. To define the mask specification for the sub-65nm device, an example of mask linearity effect is shown; MEEFs of the critical pattern designs are calculated and compared with each other; MTT, CD uniformity and MEEF relationship is commented.

In many semiconductor markets, the largest fraction of total lithography cost is photomask cost; therefore any improvements in that area can have a noticeable impact on net chip cost. A significant yield loss mechanism for advanced photomasks is through nonrepairable defects. Providing improved methods to repair defects allows for improvements in mask yield and, therefore, the cost to make a defect-free mask and eventually the cost to produce the integrated circuit. However, the connection between mask yield and integrated circuit price is not a first-order relationship because it bridges between the mask supplier and end-user. SEMATECH and other worldwide consortia have, in the past, bridged this gap by sponsoring programs to develop improved mask infrastructure tools. A significant investment has been made in mask repair tool technology, but the quantitative benefit and return on investment has not been summarized until now. This paper attempts to show the strong benefits to the photomask and semiconductor industries from improving mask repair.

A well-known recipe for reducing mask cost component in product development is to place non-redundant elements of layout databases related to multiple products on one reticle plate [1,2]. Such reticles are known as multi-product, multi-layer, or, in general, multi-IP masks. The composition of the mask set should minimize not only the layout placement cost, but also the cost of the manufacturing process, design flow setup, and product design and introduction to market. An important factor is the quality check which should be expeditious and enable thorough visual verification to avoid costly modifications once the data is transferred to the mask shop. In this work, in order to enable the layer placement and quality check procedure, we proposed an algorithm where mask layers are first lined up according to the price and field tone [3]. Then, depending on the product die size, expected fab throughput, and scribeline requirements, the subsequent product layers are placed on the masks with different grades. The actual reduction of this concept to practice allowed us to understand the tradeoffs between the automation of layer placement and setup related constraints. For example, the limited options of the numbers of layer per plate dictated by the die size and other design feedback, made us consider layer pairing based not only on the final price of the mask set, but also on the cost of mask design and fab-friendliness. We showed that it may be advantageous to introduce manual layer pairing to ensure that, e.g., all interconnect layers would be placed on the same plate, allowing for easy and simultaneous design fixes. Another enhancement was to allow some flexibility in mixing and matching of the layers such that non-critical ones requiring low mask grade would be placed in a less restrictive way, to reduce the count of orphan layers. In summary, we created a program to automatically propose and visualize shuttle mask architecture for design verification, with enhancements to due to the actual application of the code.

Nano-imprint lithography (NIL) is expected as one of the candidates for hp32nm to hp22nm technology nodes. NIL needs 1X patterns on masks and a transit from 4X to 1X means a big and hard technology jump for the mask industry. We have reported in previous papers that the resolution limit with 50keV acceleration voltage VSB (variable shaped beam) electron beam writer, which are used in current 4X photomask manufacturing, was around 65nm. And we have also reported that to reach the required resolution for hp32nm node, the usage of a 100keV acceleration voltage spot beam writer would be inevitable. Recently, we have installed a 100keV spot beam EB writer adjacent to our photomask manufacturing line. In this paper, we will present our initial results with the tool. We have confirmed, after tuning of our process, a stable resolution capability compatible for hp32nm. With this process, we have begun sample template manufacturing, and initial imprint results are also presented. Templates with hp28nm dense line patterns were fabricated and were well imprinted.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FIL^TM) is a unique method for printing sub-100 nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. With respect to inspection, although defects as small as 70 nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. The challenge is in inspecting templates composed purely of fused silica. This paper reports the inspection of both fused silica wafers and plates. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Fused silica plates were inspected using an NGR4000 system. Three different experiments were performed. In the first study, Metal 1 and Logic patterns as small as 40 nm were patterned on a 200 mm fused silica wafer. The patterns were inspected using an NGR2100 die-to-database inspection system. In the second experiment, a 6025 fused silica plate was employed. Patterns with a limited field of view (FOV) were inspected using an NGR4000 reticle-based system. To test the tool's capability for larger FOVs, 16 × 16 μm areas on a MoSi half tone plate were scanned and stitched together to evaluate the tool's ability to reliably do die-to-database comparisons across larger inspection areas.

This is a report on a panel discussion in Photomask Japan held on April 19, 2006. We discussed mask technologies for extreme ultraviolet lithography (EUVL). Seven panelists presented their views on critical issues in the production of practical EUV masks. The wrap-up is as follows: A local polishing method has yielded an average flatness of 70 nm, but it increases both surface roughness and defect density. Regarding defect density, the large gap between the target and the one expected from the learning curve led to the proposal of realistic (i.e., relaxed) specifications for flatness and defect density. The capability of detecting defects with a PSL equivalent size of 25 nm or less remains an issue. It was also suggested that the local slope of the back surface of blanks (masks) should be standardized. Mask patterning has already been demonstrated to be sufficient for the 32-nm half pitch node. Captive and commercial mask shops are ready to provide masks for full-field exposure tools. Regarding handling and shipping, dual-pod type carriers and robotic handling have been demonstrated to adequately protect masks from particle contamination. Finally, a 3-point support method in EB writing was examined in conjunction with a new EB correction scheme.

In the framework of the European EXTUMASK project, the Advanced Mask Technology Center in Dresden (AMTC) has established in close collaboration with the Institute of Microelectronics in Stuttgart (IMS-Chips) an integrated mask process suited to manufacture EUV masks for the first full field EUV scanner, the ASML α-demo tool. The first product resulting from this process is the ASML set-up mask, an EUV mask designed to realize the tool set-up. The integrated process was developed based on dummy EUV blank material received from Schott Lithotec in Meiningen (Germany). These blanks have a TaN-based absorber layer and a SiO₂ buffer layer. During process development the e-beam lithographic behaviour as well as the patterning performance of the material were studied and tuned to meet first EUV mask specifications. For production of the ASML set-up mask the new process was applied to a high performance EUV blank from Schott Lithotec. This blank has absorber and buffer layers identical to the dummy blanks but a multilayer is embedded which is deposited on an LTEM substrate. The actinic behaviour of the multilayer and the flatness of the substrate were tuned to match the required mask specifications. In this article we report on the development of the mask manufacturing process and show performance data of produced EUV full field scanner masks. Thereby, special attention is given to the ASML set-up mask.

A new thin mask model for transmission through EUV absorber features is proposed, which, when linked to an EUV buried defect simulator, can rapidly assess a buried defect's impact on the printability of nearby features. The underlying physics of an absorber edge scattering is thoroughly investigated and simplified models for two of the key physical effects are shown to produce excellent results when compared to FDTD edge scattering. By simply adding calibrated line sources to the top corners of the absorber edges, as well as propagating the thin mask by about half the mask thickness, a greatly simplified model for feature transmissions is produced. The simplified model effectively converts the electrically thick nature of the absorber patterns (~70nm or ~5λ thick) into a thin mask model, while capturing all of the appropriate effects that are demonstrated in the far field image. Line and space example patterns for dense 32nm, 22nm, and 15nm features (on wafer) demonstrate the accuracy of the new thin mask model for even very tight pitches.

Research and development efforts on EUV technology for the 32 nm node and beyond are progressing rapidly. Although a big concern is defect control on EUV mask blanks, control of linewidth and profile will be an important factor in acceptance of EUV technology. In this paper, we discuss the issues and strategies surrounding CD and profile metrology of EUV masks. EUV mask blanks from Hoya and Asahi Glass Company were used in this study, and were measured on a Nanometrics Atlas-M measurement tool, generating CD and profile results using Timbre Technologies' ODP analysis software. The Atlas-M tool has dual optics, enabling use of either normal incidence Reflectometry or oblique incidence Ellipsometry, either of which may be used for Scatterometry. The relative merits of each of these technologies are discussed. The complex EUV stack presents numerous challenges for metrology; the critical task is to accurately measure the optical constants of the numerous layers in the stack. The multilayer MoSi stack is effectively modeled as a single layer for optical constants determination. Photoresist FEP171 was used for the patterning, and the CD and profile of the resist were measured, after which the absorber layer was etched. Parameters characterized in this study include photoresist CD and height, etched Absorber CD, and capping layer over etch. Correlation to top-down CD-SEM, cross-sectional SEM, and AFM is reported. No charging or other deformation was observed on the EUV masks. The data show that ODP Scatterometry provides a non-destructive method for monitoring resist CD and profile, as well as etched structure CD and over/underetch on EUV masks.

Recent rapid progress in the technologies of extreme ultraviolet lithography (EUVL) is ensuring that EUVL will be a primary candidate for the next generation lithography beyond 32-nm node. However, realization of defect-free reflective mask blank is still counted as one of the most critical issues for high volume production in EUVL. Asahi Glass Company (AGC) has developed comprehensive technologies for manufacturing EUVL mask blanks from figuring and polishing glass substrate to cleaning, multilayer coating, and evaluating its performances by making use of our long and wide experience in providing high quality processed glass substrates and coatings for electronic devices. In this paper, we will present the current status of each aspect of EUVL mask blank development in AGC toward the specifications required for high volume production. In the effort to meet the specifications, we have introduced a number of key technologies that can be divided into three regions, which are materials, glass processings, and evaluations. We have developed state-of-the-art processes and tools for manufacturing EUV mask blanks, such as a new polishing technique for extremely flat substrate, a new cleaning recipe and tool for low-defect substrate, and a newly developed deposition tool for ultra-low defect and higher EUV reflective coating with our new optical thin film materials for multilayer coating. Furthermore, in order to clarify their performances, we also introduced a wide variety of evaluation techniques such as flatness and roughness measurement of substrate, a defect inspection, and EUV reflectometry as well as defect analysis techniques which help us eliminate printable defects in EUVL mask blanks.

The feasibility of removing defects from the surface of extreme ultraviolet (EUV) substrates by nanomachining is being investigated. A commercially available atomic force microscope (AFM) based photomask repair tool was used. A specific class of defects which has resisted all other removal techniques was targeted. Three AFM probes of varying sharpness were evaluated. All of the probes removed the majority of each but fell short of achieving the desired 2006 high spatial frequency roughness specification of 0.2nm. Results reported are preliminary; future work will focus on optimization of scanning parameters and tip geometry targeting specific residual defects reported in the text.

As the design rule continues to shrink towards 45 nm node and beyond, the lithographers need the new technologies such as immersion lithography and EUV lithography. Also the inspection specification on the printed reticle defects is becoming even more challenging for the reticles used in both lithography methods. The main purpose of this study is to investigate the pattern defect detection capability on EUV mask with the memory design patterns of 45 nm node and below in the DUV reticle inspection systems at our mask-shop and to compare those results with the absorber defect specification from the EUV lithography simulation in those design rules. In addition, we investigate the inspection capability on the pattern defects with the test optical mask designed in 45 nm node and below for the immersion lithography and compare the defect detection ability on the EUV mask and the optical mask in the current DUV reticle inspection equipment.

The production of defect-free mask blanks remains a key challenge for EUV lithography. Mask-blank inspection tools must be able to accurately detect all critical defects whilst simultaneously having the minimum possible false-positive detection rate. We have recently observed and here report the identification of bump-type buried substrate defects, that were below the detection limit of a non-actinic (i.e. non-EUV) inspection tool. Presently, the occurrence of pit-type defects, their printability, and their detectability with actinic techniques and non-actinic commercial tools, has become a significant concern. We believe that the most successful strategy for the development of effective non-actinic mask inspection tools will involve the careful cross-correlation with actinic inspection and lithographic printing. In this way, the true efficacy of prototype inspection tools now under development can be studied quantitatively against relevant benchmarks. To this end we have developed a dual-mode actinic mask inspection system capable of scanning mask blanks for defects (with simultaneous EUV bright-field and dark-field detection) and imaging those same defects with a zoneplate microscope that matches or exceeds the resolution of EUV steppers.

Chromeless Phase Lithography (CPL) has been used to achieve high resolution by using phase edge interference in addition with high NA and off-axis illuminations such as annular and quasar for sub-wavelength lithography. There are two types of CPL. One is the totally chromeless pure phase type and the other is the zebra chrome pattern type for critical line dimensions. Both types of CPL masks require adding in chrome pads in some structures such as circuit line junction region to improve the resolution. Zebra type CPL mask making has reached the limitation due to small chrome peeling issue during mask cleaning and small space writing resolution issue for sub-45nm technology. In this paper, two types of CPL masks are studied. The investigation shows the differences on mask making and wafer performance. For mask making, process limitation studies such as writing, etching and cleaning will be evaluated. Data on mask CD (Critical Dimension) performance, registration, overlay, phase and transmission are collected and analyzed. For wafer performance, process window comparison, CD through pitch, MEEF (Mask Error Enhancement Factor) and linearity will be characterized for these two CPL mask types. Minimum resolution of less than 160nm pitch with reasonable good process window has been achieved with both mask types. Chromeless pure phase type has advantages on mask making while zebra type has the advantages on wafer performance. Furthermore, SRAF (Sub-Resolution Assist Feature) are added to improve wafer printing process windows. Detailed characterization work done on assist features are presented. Assist feature can improve process window by improving the contrast of isolated lines.

Recent advances in lithography simulation have made full-chip lithography rule checking (LRC) practical and even mandatory for many fabs, especially those operating with half-pitches under 100nm. These LRCs routinely identify marginal or even fatal manufacturability problems (hot-spots), especially when simulated through process corners. Until recently, when hot-spots were identified, the only options were to reject the tapeout for additional layout modifications, re-run OPC with a different recipe, or use a DRC-tool to do "blind" cut-and-paste repairs under the assumption that making fatal errors non-fatal is sufficient to make them "good." Using a commercial LRC tool, we will inspect OPC data on a production design to identify a typical volume of real and potential hot-spots. Next, using Halo-Fix from Aprio Technologies, we will apply local repairs, choosing rule-based or model-based repair strategies as appropriate for each type of hot-spot. Using this method, "intelligent" changes in the hot-spot areas can be made which accurately account for lithography interactions and process variations, in order to optimize for manufacturing robustness. To verify that the repairs are acceptable, LRCs will be performed and the results analyzed.

A novel mask structure for an alternating aperture phase shift mask (Alt-PSM) to cut mask cost is proposed. By a mask with structure of an embedded attenuating phase shift mask (Atten-PSM), an Alt-PSM for an isolated line formation can be well fabricated. Fine image quality is confirmed with optical image calculations. Moreover, concept of this novel mask is proved by a preliminary experiment. In conclusion, this novel mask can replace conventional Alt-PSM for logic devices, resulting in considerable cut of mask cost.

In the semiconductor industry, control of ammonia at the parts-per-billion concentration level is critical to insure the integrity of the lithography process. Ammonia is emitted into wafer fab air by various semiconductor processes including CVD, wafer cleaning, coater tracks, and CMP, as well as from outdoor air. Exposure to even low parts-per-billion concentrations of ammonia during the photolithography process can lead to yield loss and unscheduled equipment downtime. Picarro, Inc. has developed a field-deployable, real time, ambient gas analyzer capable of continuously monitoring parts-per-trillion levels of ammonia in situ, and in real-time, thereby allowing a user to directly monitor ammonia levels in sensitive photo-lithography equipment.

We created haze defects on the PSM mask surface using ArF haze accelerator while the mask was previously cleaned by SPM and SC1 solutions. Then we directly analyzed the defects on the surface using TOF-SMS. The comprehensive analysis of TOF-SIMS signifies that the defects mainly consist of hydrocarbons, Na, K, Cl, F, Mg, Al, etc., which have probably come from previous procedures, fab environments, storage materials, handling steps, or pellicle materials. This fact implies the exclusion of sulfate or ammonium ions from the mask surface should not be enough for the realization of haze-free PSM masks. In addition, complete removal of residual hydrocarbons deposited through previous procedures and perfect protection against environmental contaminants from fab air, storage materials, handling steps, or pellicle materials should be further accomplished.

Each generation of semiconductor device technology drives many new and interesting resolution enhancement technologies (RET). As minimum feature size of semiconductor devices have shrunk, the exposure wavelength has also progressively shrunk. The 193 nm lithography for low-k₁ process has increased the appearance of progressive defects on masks often known as haze or crystal growth. Crystal growth on a mask surface has become an increasing issue as the industry has adopted a 193 nm wavelength in order to increase lithographic resolution and print ever decreasing device line width. Haze is known to be a growing defect on photomask as a result of increased wafer lithography exposure and photochemical reactions induced by combination of chemical residuals on the mask surface. We build experimental system to create and detect the haze growth. A photomask is enclosed in a glove box where the atmosphere and exposure conditions are controlled and monitored throughout the exposure processing. A test photomask is exposed to accumulate the dose of laser radiation. And then spectroscopic ellipsometry and metallographic microscope techniques are used to check the surface conditions of the masks before and after the laser exposure. We found that spectroscopic ellipsometry measurement values of Δ and Ψ were changed. The results of the spectroscopic ellipsometry analysis show the change of the haze thickness on mask surface. Thickness and roughness of the mask surface is increased with the exposure. This means that haze grows on the mask surface by the exposure. Masks become useless due to transmission loss or defect generation, which is directly related to the formation of the haze. The haze causes the increase of mask thickness, transmission drop and affects the formation of pattern. So, we investigated the linewidth variation and the process window as a function of haze size effect with Solid-E of Sigma-C.

Cleaning chemistry residue in photomask manufacturing is one of root causes to generate HAZE over surface of photomask for 193nm and shorter wavelength exposure tools. In order to reduce the residue, chemical free process is one of targets in photomask industry. In this paper novel clean technology without sulfuric acid and ammonia chemical are shown to manufacture sub-90nm node photomask. Photo and E-beam resist were removed by plasma and ozone water clean instead of sulfuric acid. SPM and APM in final clean sequence before defect inspection were substituted with ozone water and hydrogen water respectively. The clean performance was demonstrated in real production of 193nm phase shift mask. Sulfate and Ammonia residue after final clean were controlled same as blank material level without any clean process.

The ability to eliminate the critical source of haze contamination which can be derived from the cleaning chemistry residues and mass production environment has become a major challenge for 193 nm photolithography in semiconductor industry. Furthermore, as the specification for pattern generation on photomask becomes tighter, it is getting harder and harder to eliminate defects with both minimal structural damage and preservation of photophysical properties. We designed for the smart cleaning strategy to achieve the defect-free photomasks as a concern of above current issue with a combination of well-known cleaning technology, such as using the collective effects of ozonated water (DIO₃) for the alternative to conventional clean (SPM/SC1) and UV/O₃ treatment for the control of sulfate concentration. In addition to photomask clean, these strategies are also used for photoresist stripping. As well as the final cleaning process, it is a rational strategy that judicious modification of inter-process clean. Specially, that kind of view is focused on the after-development clean (ADC) process which mainly eliminated the source of fatal defects on the mask, such as pattern bridge following dry etch process. In this paper we will propose a novel cleaning strategy for the elimination of potential source of haze formation and fatal defects.

Extreme ultraviolet lithography (EUVL) is being considered as the enabler technology for the manufacturing of future technology nodes (30 nm and beyond). EUV mask blanks are Bragg mirrors made of Mo and Si bilayers and tuned for reflectivity at a wavelength λ ~13 nm. Implementation of EUVL requires that the mask blanks be free of defects at 30 nm or above. However, during the deposition of MoSi multilayers and later during the handling of blanks, defects are added to the blank. Therefore, the cleaning of EUV mask blanks is a critical step in the manufacturing of future devices. The particulate defects on the multilayer-coated mask blanks can either be embedded in or under the MoSi layers or adhered to the top capping layer during the deposition process. The defects can also be added during the handling of photomasks. Our previous studies have shown successful removal of the handling-related defects at SEMATECH's Mask Blank Development Center (MBDC) in Albany, NY. However, cleaning embedded and adhered defects presents new challenges. The cleaning method should not only be able to remove the particles, but also be compatible with the mask blank materials. This precludes the use of any aggressive chemistry that may change the surface condition leading to diminished mask blank reflectivity. The present work discusses the recent progress made at SEMATECH's MBDC in cleaning backside Cr-coated mask blanks with a MoSi multilayer and a Si cap layer on the top surface. Here we present our data that demonstrates successful removal of sub-100 nm particles added by the deposition process. Surface morphology and defect composition on the surface of the MoSi multilayer are discussed. EUV reflectivity measurements and atomic force microscopy (AFM) images of the mask blank before and after cleaning are presented. The present data shows that no measurable damage to the EUV mask blank is caused by the cleaning processes developed at the MBDC.

Photomasks with various sub resolution assist feature (SRAF) were vigorously cleaned by a megasonic tool, and their pattern damage, "SRAF-missing", was investigated. As a result, it was found that SRAF-missing can occur at a low probability by the megasonic cleaning and the probability significantly depends on SRAF size, especially width. With smaller than 100 nm width, SRAF-missing probability rapidly increased with SRAF width reduction. In addition, the relationship between SRAF-missing and acoustic pressure was investigated, and at the same time that between particle removal efficiency (PRE) and acoustic pressure was also investigated. As a result, SRAF-missing and PRE showed a trade-off relationship. Using all results, an experimental equation was provided. After verification by additional experiments, some simulations were done, and megasonic cleaning subject was predicted for the 45nm and 32nm-node mask fabrication.

As the advent of advanced process technology such as 65nm and below, the designs become more and more sensitive to the variation of manufacturing process. Though the complicated design rules can guarantee process margin for the most layout environments, some layouts that pass the DRC still have narrow process windows. An effective layout optimization approach based on Litho Friendly Design (LFD), one of Mentor Graphics' products, was introduced to enhance design layout manufacturability. Additional to process window models and production proven Optical Proximity Correction (OPC) recipes, the LFD design kits are also generated and needed, which with the kits and rules people should guarantee no process window issues in a design if the design passes the check of these rules via the kits. Lastly, a real 65nm product Metal layer was applied full chip OPC and post-OPC checks to process variation. Some narrow process window layouts were detected and identified, then optimized for larger process window based on the advices provided by LFD. Both simulation and in-line data showed that the DOFs were improved after the layout optimization without changing the area, timing and power of the original design.

Recent work has shown that bimetallic films, such as Bi/In and Sn/In, can create laser direct-write grayscale photomasks. Using a laser-induced oxidation process; bimetallic films turn transparent with variations in optical transparency that are a function of the laser power. The films exhibit transmittances <0.1% when unexposed and >60% when full laser exposed. A novel grayscale photolithography technique is presented that utilizes conventional chrome photomasks as the high resolution pattern-defining layer with a bimetallic thin film layer deposited on top as the grayscale-defining layer. Having the grayscale layer on top of the chrome, grayscale patterns can be aligned to the underlying chrome patterns. Laser power and bimetallic thin film thickness are carefully calibrated such that no chrome ablation or conversion occurs. The calibration ensures that during laser scanning, the bottom chrome layer defines the fine features of the underlying patterns and remains unchanged, while the bimetallic thin film layer is converted to provide grayscale tones. To further investigate the optical density (OD) properties of this type of mask, we measured the transient time response for pure chrome mask and Bi/In coated chrome mask to help fine tune the laser writing parameters. Using bimetallic Bi/In/Cr photomasks, we have successfully created continuous tone 3D structures with superimposed binary structures in SU-8 photoresist. By introducing this novel combined chrome-bimetallic mask, the fine detail features found in binary lithography may be combined with smoothly-varying 3D microstructures best suited to grayscale methods.

As technology advances towards 45nm node and beyond, optical lithography faces increased challenges and resolution enhancement techniques (RET) are imperative for multiple process layers and poly-silicon gate layer in particular. With RET implementation, and optical proximity correction (OPC) techniques, the mask layout deviates further away from design intended layout. For an OPC decorated design database, it is important that before mask making, the OPC is verified that it is design related defects free and provides reasonable process window for a given process to ensure manufacturability. For poly-silicon gate layer, due to tight CD control requirement, the demand for accurate lithography process simulation is even greater. As hyper-NA immersion exposure systems become available, accurate resist image computation considering mask topography effects and partial polarized illumination on poly-silicon gate layers through process window is a necessary. In this work, we will show simulation results of DesignScan on an advanced poly-silicon gate layer using a logic based customer database. Active layer database is used to separate poly-silicon gate regions and poly-silicon wire regions. Sensitive CD and edge placement error (EPE) detectors are used to identify design related defects through the lithography process window. The detector sensitivities can be adjusted based on feature sizes and their geometry (gate of different targets or wires, corners, and line ends). This customization of geometry classification and detector sensitivity is critical to achieve desired through process window inspections. With this capability process window inspections will show how CD/EPE changes as functions of exposure dose and defocus with fast results and efficient review and disposition. Accurate process window assessment using CD variation is obtained.

Requirements to meet the 45nm technology node place significant challenges on Mask makers. Resolution Enhancement Techniques (RET) employed to extend optical lithography in order to resolve sub-resolution features, have burdened mask processes margins. Also, Yield compromises loom with every nanometer of error incurred on the Mask and the Device platforms. RET techniques, such as Optical Proximity Correction (OPC), require the Mask Etcher to achieve exceptionally tight control of Critical Dimensions (CD). This ensures OPC feature integrity on the mask and resultant image fidelity of OPC structures, as well as, subsequently high and sustainable yields. This paper talks about 45 nm Chrome etch challenges and how Applied Materials next generation mask etcher provides solutions to these challenges.

One means of extending the limits and lifetime of current lithography platforms for 45nm and beyond is the development of resolution enhancement techniques (RET) in the form of optical phase-shifting masks (PSM). By employing optical interference from 180° shifted lithography emission, PSM masks are able to enhance feature resolution at the wafer. This is particularly important for sub-wavelength features (i.e., features with critical dimensions less than the lithography wavelength) where line resolution can be severely degraded without such techniques. For these PSMs, the challenge is to provide highly uniform quartz etch performance across the entire active area of the mask for various feature sizes and local loads. Micro-loading (a.k.a. RIE lag or reactive ion etch lag) and phase angle range are key performance parameters to control. As the demands for these parameters tighten and mask costs rise, strict performance control is required for all PSM mask varieties utilized in the mask shop. In this paper we will discuss process results using Applied Materials next generation mask etch system in the area of APSM etch application. In particular, the discussion will focus on recent process results in phase uniformity and RIE lag for Quartz etch process. Feature profiles are also discussed with examples showing near vertical sidewalls and no micro-trenching.

To control the CD precisely, inorganic "Hard-Mask" which we expect one of the candidates for 45nm-node and beyond technology was evaluated. Hard-Mask which is inserted between resist and Cr layer of a photomask blank enable us to use high anisotropic etch condition. Also it enhances the resist resolution because it can avoid the interaction between resist and Cr. This time, we confirmed the benefit of Hard-Mask which could reduce the etch bias and proximity process error. Especially proximity process error was reduced down to 1/4. And resolution enhancement effect was observed. We also confirmed the blank quality such as defects, film stress, sheet resistance, optical properties and so on, and found that Hard-Mask blank would not be a showstopper for this development.

The CD requirements for the 45nm-node will become tighter so as it will be difficult to achieve with 65nm node technologies. In this paper, a method to improve resolution by using DRECE (Dry-etching Resistance Enhancement bottom-Coating for Eb) will be described. After all, DRECE has five times as high dry-etch resistance than the EB resist, and this enables to accept higher anisotropic dry etching condition. By optimizing dry etching conditions, the CD iso-dense bias dropped to 1/3 and the CD shift was reduced to 1/2. Also, there was no negative effect to CD uniformity. From these results, we propose the use of DRECE for the 45nm-node technology.