20 October 2006 A generic method for the detection of electrically superfluous layout features
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Abstract
"Sub-resolution assist features" (SRAFs) are a standard "resolution enhancement technique" (RET) to ensure the lithography process window of narrow lines for critical mask levels. Since placement rules for SRAFs commonly demand a fixed, constant separation from the edges of the main features to be assisted, small jogs and notches in the layout of the main features force an SRAF interruption. As a consequence, locally the process window is reduced. In addition, jogs and notches increase the data amount and may cause an increase of run time of "design rule check" (DRC), "optical proximity correction" (OPC), and "mask data preparation" (MDP). In most cases, these jogs and notches are completely unnecessary for the electrical functionality of the circuit and the design rule compliance of the layout. In order to detect such superfluous layout features and give the physical designer the opportunity to remove them, a new approach to design rule checking was developed. This approach is based on the decomposition of the layout of one mask level into its basic geometrical features (e.g., corners, line ends, junctions) and a subsequent classification of these features according to their topology under consideration of electrically related other mask levels (e.g., metal + via = contact pad). We describe the implementation of a generic DRC for the detection of jogs and notches using this approach and highlight the stability and ease of maintenance of this method.
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Markus Hofsaess, Markus Hofsaess, Thomas Roessler, Thomas Roessler, Eva Nash, Eva Nash, } "A generic method for the detection of electrically superfluous layout features", Proc. SPIE 6349, Photomask Technology 2006, 634916 (20 October 2006); doi: 10.1117/12.687856; https://doi.org/10.1117/12.687856
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