With moving from one process node to another, process effect corrections are becoming a very challenging task. High
quality models, long run times and extensively large computer resources are needed to perform a typical modern process
effect correction procedure. Since the patterns that form IC layouts are highly repetitive, all the modern process
correction algorithms try to take advantage of this fact to decrease processing time and computer resources requirements.
However, currently used high accuracy process effect correction algorithms are becoming less and less advantageous
because of the increasing relative non-locality of the process effects. In this paper, we investigate the feasibility of a
simpler approach called "cell-wise corrections". We propose a recipe for the cell-wise process effect correction and analyze its accuracy using a 65 nm test layout. The recipe is fully automated and implemented using a commercially
available OPC tool. The analysis reveals good accuracy and feasibility of our approach.