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20 October 2006 Alternating PSM for sub-60-nm DRAM gate single exposure
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Abstract
The fast pattern shrinkage of DRAM has driven the lithography technology into the low k1 regime for sub-60 nm technology node. There are a lot of resolution enhancement techniques (RETs) e.g. OPC (Optical Proximity Correction), SB (Scattering Bar), SRAF (Sub-Resolution Assist Features) and DDL (Double Dipole Lithography) and Alternating PSM to enable the low k1 lithography [4]. However, among the RETs, the alternating PSM technique is a high cost solution because double exposure is needed to avoid phase conflict error. Therefore, the implementation of alternating PSM with single exposure for gate conductor layer is the main purpose of this study. Many kinds of pattern and phase designs in the main cell and periphery were investigated.
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Kunyuan Chen, Richard Lu, Kuo Kuei Fu, ChungPing Hsia, Chiang-Lin Shih, and JengPing Lin "Alternating PSM for sub-60-nm DRAM gate single exposure", Proc. SPIE 6349, Photomask Technology 2006, 63491T (20 October 2006); https://doi.org/10.1117/12.685295
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