In the photo-lithography process, a mask is one of the most important items because CD error from its imperfection is
transferred to the CD error on the wafer. And the CD error amplification from the mask CD to the wafer CD is denoted
by Mask Error Enhancement Factor (MEEF).
As the device shrinks so fast, MEEF increases conspicuously and massive OPC is necessary to secure the target
pattern CD and the proper process margin on the wafer. Therefore the mask CD uniformity and the just mean-to-target
(MTT) are very important to minimize the CD variation on the wafer level.
In most cases, MTT and CD uniformity for a certain device are not defined exactly. What we know is that the smaller,
the better. Because just small value of MTT and CD uniformity is not the reasonable guideline for the mask fabrication
and inducing high mask cost, defining the logical MTT and CD uniformity prospect for a certain device or layer is very
As the necessity of the low k1 process increases, MTT and CD uniformity specifications become tighter and tighter.
However the proper mask specification for sub-65nm real device has not been defined yet and not been studied
considering the mask fabrication and MEEF.
In this study, MTT and CD uniformity specification of the sub-65nm real device patterns are discussed with respect to
the mask pattern linearity and MEEFs. Mask linearity is one of the typical items for the mask fabrication and strongly
related to MTT and CD uniformity. MTT and CD uniformity tolerance also follows OPC tolerance, and OPC tolerance is
directly related to the pattern layouts and MEEF. To define the mask specification for the sub-65nm device, an example
of mask linearity effect is shown; MEEFs of the critical pattern designs are calculated and compared with each other;
MTT, CD uniformity and MEEF relationship is commented.