Translator Disclaimer
Paper
20 October 2006 EUV mask pattern inspection for memory mask fabrication in 45-nm node and below
Author Affiliations +
Abstract
As the design rule continues to shrink towards 45 nm node and beyond, the lithographers need the new technologies such as immersion lithography and EUV lithography. Also the inspection specification on the printed reticle defects is becoming even more challenging for the reticles used in both lithography methods. The main purpose of this study is to investigate the pattern defect detection capability on EUV mask with the memory design patterns of 45 nm node and below in the DUV reticle inspection systems at our mask-shop and to compare those results with the absorber defect specification from the EUV lithography simulation in those design rules. In addition, we investigate the inspection capability on the pattern defects with the test optical mask designed in 45 nm node and below for the immersion lithography and compare the defect detection ability on the EUV mask and the optical mask in the current DUV reticle inspection equipment.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Do Young Kim, Seong Yong Cho, Hun Kim, Sung Min Huh, Dong Hoon Chung, Byung Chul Cha, Jung Woo Lee, Seong Woon Choi, Woo Sung Han, Ki Hun Park, Eun Ji Kim, Zhengyu Guo, Ellen Quach, David Gee, Tom Brown, and Aditya Dayal "EUV mask pattern inspection for memory mask fabrication in 45-nm node and below", Proc. SPIE 6349, Photomask Technology 2006, 63492L (20 October 2006); https://doi.org/10.1117/12.686488
PROCEEDINGS
10 PAGES


SHARE
Advertisement
Advertisement
Back to Top