As for 32-nm node (minimum half pitch 45-nm) logic device of the next generation, the leading semiconductor
device makers propose the following three kinds of lithography techniques as a candidate, multi-exposure with water
immersion lithography. So we will evaluate them.
In previous work, we evaluated the resolution limit and printing performance through various pitches of 45-nm
node (minimum half pitch 65-nm) lithography. We evaluated the alternate aperture phase shift mask(alt-PSM) of NA=0.93
(dry and immersion) and various resolution enhancement technologies (RETs) with off-axis and polarized illumination of
NA=1.07(water immersion). The minimum k1 examined at previous time was 0.31 and 0.39 respectively. To achieve 32-nm
node of the next generation with water immersion lithography, we must use higher NA but yet severe k1. The combination
of the strong RET, polarization and multi-exposure is thought to be required. In order to resolve severe k1 (<0.3), the double
patterning is thought as a promising candidate technology, though the disadvantageous points will appear such as very
severe alignment accuracy and the twice process of wafer. In this report, we will discuss some RETs such as double dipole
lithography(DDL), double patterning lithography(DPL) and alt-PSM that have sufficient printing performance through
various pitches of 32-nm node. We evaluate the effect and the performance of the selected lithography side RETs and mask
material RETs for each, using optical simulation software.