The runtime of model-based optical proximity correction (OPC) tools has grown unacceptably with each successive
technology generation, and has emerged as one of the major bottlenecks for turnaround time (TAT)
of IC data preparation and manufacturing. The cell-based OPC approach improves runtime by performing
OPC once per cell definition as opposed to once per cell instantiation in the layout. However, cell-based OPC
does not comprehend inter-cell optical interactions that affect feature printability in a layout context. In this
work, we propose auxiliary pattern-enabled cell-based OPC which can minimize the CD differences between
cell-based OPC and model-based OPC. To enable effective insertion of auxiliary pattern (AP) in the design,
we also propose a post-placement optimization of a standard cell block with respect to detailed placement.
By dynamic programming-based placement perturbation, we achieve 100% AP applicability in designs with
placement utilizations of < 70%. In an evaluation with a complete industrial flow, cell-based OPC with AP
can match gate edge placement error (EPE) count of model-based OPC within 4%. This is an improvement of
90%, on average, over cell-based OPC without APs. The AP-based OPC approach can reduce OPC runtimes
versus model-based OPC by up to 40X in our benchmark designs. We can also achieve reduction of GDSII file
size and ORC runtimes due to hierarchy maintenance of cell-based OPC.