Illumination optimization for 65nm technology node

Ching-Heng Wang; Qingwei Liu; Liguo Zhang; Chi-Yuan Hung

doi:10.1117/12.685077

20 October 2006 Illumination optimization for 65nm technology node

Ching-Heng Wang, Qingwei Liu, Liguo Zhang, Chi-Yuan Hung

Proceedings Volume 6349, Photomask Technology 2006; 63494V (2006) https://doi.org/10.1117/12.685077
Event: SPIE Photomask Technology, 2006, Monterey, California, United States

Abstract

The most important task of the microlithography process is to make the manufacturable process latitude/window, including dose latitude and Depth of Focus, as wide as possible. Thus, to perform a thorough source optimization during process development is becoming more critical as moving to high NA technology nodes. Furthermore, Optical proximity correction (OPC) are always used to provide a common process window for structures that would, otherwise, have no overlapping windows. But as the critical dimension of the IC design shrinks dramatically, the flexibility for applying OPC also decreases. So a robust microlithography process should also be OPC-friendly. This paper demonstrates our work on the illumination optimization during the process development. The Calibre ILO (Illumination Optimization) tool was used to perform the illumination optimization and provided plots of DOF vs. various parametric illumination settings. This was used to screen the various illumination settings for the one with optimum process margins. The resulting illumination conditions were then implemented and analyzed at a real wafer level on our 90/65nm critical layers, such as Active, Poly, Contact and Metal. In conclusion, based on these results, a summary is provided highlighting how OPC can get benefit from proper illumination optimization.

Citation Download Citation

Ching-Heng Wang, Qingwei Liu, Liguo Zhang, and Chi-Yuan Hung "Illumination optimization for 65nm technology node", Proc. SPIE 6349, Photomask Technology 2006, 63494V (20 October 2006); https://doi.org/10.1117/12.685077

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