Architecture design of real-time dual-ring optical industrial Ethernet and its FPGA implementation

Wentao Chen; Depeng Jin; Lieguang Zeng

doi:10.1117/12.688001

28 September 2006 Architecture design of real-time dual-ring optical industrial Ethernet and its FPGA implementation

Wentao Chen, Depeng Jin, Lieguang Zeng

Proceedings Volume 6354, Network Architectures, Management, and Applications IV; 63542E (2006) https://doi.org/10.1117/12.688001
Event: Asia-Pacific Optical Communications, 2006, Gwangju, South Korea

Abstract

Ethernet has been a hotspot in industrial communication. Its intrinsic non-determinism and slow failure recovery mechanism are two major obstacles of Ethernet's application in the industrial environment. To address these two problems, this paper proposes a novel fast recovery and real-time optical industrial Ethernet architecture based on dual-ring topology, and presents some test results from our partly implementation of the architecture. First, resource utlilization of the FPGA implementation shows that the proposed architecture is cost effective. Second, it is seen that recovering from a single failure costs no more than 30 ms, far less than traditional resilience techniques in Ethernet. Besides, end to end delay with no background traffic, which is instructive to the future design of the scheduling algorithms, is also presented.

Citation Download Citation

Wentao Chen, Depeng Jin, and Lieguang Zeng "Architecture design of real-time dual-ring optical industrial Ethernet and its FPGA implementation", Proc. SPIE 6354, Network Architectures, Management, and Applications IV, 63542E (28 September 2006); https://doi.org/10.1117/12.688001

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