30 October 2006 Design and implementation of high-speed digital CMOS camera driving control timing and data interface
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Abstract
High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera, the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) × 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition, these functions that adjustments of exposure beginning time, integral time, AOI (Area of Interest) output and so on, are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip), and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate, low power, intelligent and miniaturization digital video camera.
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Honghai Sun, Rongtai Cai, Yanjie Wang, "Design and implementation of high-speed digital CMOS camera driving control timing and data interface", Proc. SPIE 6358, Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control, and Computer Simulation, 63580C (30 October 2006); doi: 10.1117/12.717638; https://doi.org/10.1117/12.717638
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