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30 October 2006 Behavioral modeling to circuit design steps of switched-current second order sigma-delta modulator
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Abstract
In this paper the design and simulation procedure of a A 3.3 V, 10 Bits Switched-Current Second Order Sigma-Delta Modulator is discussed. The circuit non-idealities of the modulator such as charge injection errors, conductance ratio error, settling error and kT/C noise are modeled behaviorally using SIMULINK. For each model we present a description of the relationship between error and parameters of MOS FET, and those non-idealities have been transformed to currents. The required circuit specifcations are extracted from the behavioral simulation results. In order to get 10-bits of resolution for a 8-KHz signal bandwidth. an optimum choice was a second order modulator with an over-sampling ratio of 128 and sampling frequency of 2.048Mz. To test the design procedure validity the modulator has been designed with full differential switched current integrators in a 0.35pm double poly, four metal CMOS process. Circuit simulations indicated 50dB of peak SNDR from a single 3.3Vsupply and 18mW power consumption.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jierong Guo, Yigang He, Shengxue Tang, and Hongmin Li "Behavioral modeling to circuit design steps of switched-current second order sigma-delta modulator", Proc. SPIE 6358, Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control, and Computer Simulation, 635853 (30 October 2006); https://doi.org/10.1117/12.718256
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