A data management layer for parallel matrix computation

Adam Burdeniuk; Kiet To; Cheng Chew Lim

doi:10.1117/12.695626

5 January 2007 A data management layer for parallel matrix computation

Adam Burdeniuk, Kiet To, Cheng Chew Lim

Proceedings Volume 6414, Smart Structures, Devices, and Systems III; 641412 (2007) https://doi.org/10.1117/12.695626
Event: SPIE Smart Materials, Nano- and Micro-Smart Systems, 2006, Adelaide, Australia

Abstract

Real-time signal processing and control applications are commonly expressed in terms of matrix or vector algorithms. This paper presents a novel decoupled architecture for these algorithms. The matrix data management layer (MDML) architecture presented separates data processing from data management. It implements functions for memory sequencing and inter-processor communications that are tuned for matrix applications. This separation allows greater flexibility in the choice of data processor to find a suitable trade-off in speed, core size, power consumption and functionality.

Citation Download Citation

Adam Burdeniuk, Kiet To, and Cheng Chew Lim "A data management layer for parallel matrix computation", Proc. SPIE 6414, Smart Structures, Devices, and Systems III, 641412 (5 January 2007); https://doi.org/10.1117/12.695626

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