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9 February 2007 Active silicon components for chip to chip interconnects
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Among the major challenges confronting the current initiatives to incorporate optical interconnect capabilities for chip to chip I/O is to define, develop and implement the necessary components required for a complete pipeline from source to receiver. For next generation integrated circuits, the need for multifunctionality and multidimensional integration has resulted in new demands on interface technology to yield massively parallel data and clock lines. At this point, such methods are primarily limited to static reflectors, filters and gratings for interface and optical routing. One of the crucial elements is to develop a high performance and flexible optical network to transform an incoming optical pulse train into a widely distributed set of optical signals whose direction, alignment and power can be independently controlled. This coupling can be achieved using several methods including active (primarily, MEMS-based) beam steering arrays. For chip to chip applications, the overwhelming majority of the recent research and development effort has been focused on source and detector technologies, but less attention has been devoted to flexible, reconfigurable beam steering modalities. A variety of approaches for such beam steering and distribution of both timing and data lines has been examined. This paper will present an overview of active, silicon components under development at the College of Nanoscale Science and Engineering for arraybased I/O management with an emphasis on reconfigurable diffractive devices and adjustable, porous silicon- based components which combine optical beam steering, filtering and focusing capabilities. Design details along with initial performance data from prototype components will be presented.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
James Castracane, Natalya Tokranova, and Da Song "Active silicon components for chip to chip interconnects", Proc. SPIE 6477, Silicon Photonics II, 647704 (9 February 2007);

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